February 2022 Archives by subject

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Starting: Tue Feb 1 00:20:46 GMT 2022
Ending: Mon Feb 28 15:54:30 GMT 2022
Messages: 340

• [Bug] DWARF-5 section names in PE/PEP and weak symbols   Achim Gratz
• [Bug] DWARF-5 section names in PE/PEP and weak symbols   ASSI
• [Bug] DWARF-5 section names in PE/PEP and weak symbols   Achim Gratz
• [Bug] DWARF-5 section names in PE/PEP and weak symbols   Achim Gratz
• [Bug] DWARF-5 section names in PE/PEP and weak symbols   Achim Gratz
• [CFP] Binary T00ls Summit 2022   Jose E. Marchesi
• [CFP] Binary T00ls Summit 2022   Thomas Schwinge
• [CFP] Binary T00ls Summit 2022   Jose E. Marchesi
• [PATCH 0/1] RISC-V: Fix RV32Q conflict   Tsukasa OI
• [PATCH 0/1] RISC-V: Fix RV32Q conflict   Jan Beulich
• [PATCH 0/1] RISC-V: Fix RV32Q conflict   Tsukasa OI
• [PATCH 0/2] x86/x32: relocation overflow detection   Jan Beulich
• [PATCH 0/3] disassembler syntax highlighting in objdump (via libopcodes)   Andrew Burgess
• [PATCH 0/3] disassembler syntax highlighting in objdump (via libopcodes)   Nelson Chu
• [PATCH 0/3] disassembler syntax highlighting in objdump (via libopcodes)   Andrew Burgess
• [PATCH 0/3] RISC-V: Add CSRs for several supervisor extensions   Tsukasa OI
• [PATCH 0/3] RISC-V: Make ISA parser stricter (with code clarity improvement)   Tsukasa OI
• [PATCH 0/4] PR28824, relro security issues   Alan Modra
• [PATCH 0/4] RISC-V: Zfinx fixes/enhancements: Part 3   Tsukasa OI
• [PATCH 0/5] RISC-V: Add Ratified Cache Management Operation ISA Extensions (with paren)   Tsukasa OI
• [PATCH 0/5] RISC-V: Zfinx fixes/enhancements: Part 1   Tsukasa OI
• [PATCH 1/1] RISC-V: Fix mask for some fcvt instructions   Nelson Chu
• [PATCH 1/1] RISC-V: Fix RV32Q conflict   Tsukasa OI
• [PATCH 1/2] Revert "PR28824, relro security issues, x86 keep COMMONPAGESIZE relro"   H.J. Lu
• [PATCH 1/2] RISC-V: Don't report mismatch warnings when versions are larger than 1.0.   Aurelien Jarno
• [PATCH 1/2] RISC-V: Don't report mismatch warnings when versions are larger than 1.0.   Palmer Dabbelt
• [PATCH 1/2] x86: don't suppress overflow diagnostics in x32 mode   Jan Beulich
• [PATCH 1/2] x86: don't suppress overflow diagnostics in x32 mode   H.J. Lu
• [PATCH 1/3] objdump/opcodes: add syntax highlighting to disassembler output   Andrew Burgess
• [PATCH 1/3] objdump/opcodes: add syntax highlighting to disassembler output   Tom Tromey
• [PATCH 1/3] RISC-V: Add 'Smstateen' extension and its CSRs   Tsukasa OI
• [PATCH 1/3] RISC-V: Add 'Smstateen' extension and its CSRs   Nelson Chu
• [PATCH 1/3] RISC-V: Add 'Smstateen' extension and its CSRs   Tsukasa OI
• [PATCH 1/3] RISC-V: Add 'Smstateen' extension and its CSRs   Tsukasa OI
• [PATCH 1/3] RISC-V: Remove a loop in the ISA parser   Tsukasa OI
• [PATCH 1/3] RISC-V: Remove a loop in the ISA parser   Nelson Chu
• [PATCH 1/4] PR28824, relro security issues   Alan Modra
• [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs   Tsukasa OI
• [PATCH 1/4] RISC-V: Add assembler testcases for Zdinx regs   Palmer Dabbelt
• [PATCH 1/5] RISC-V: Add mininal support for Zicbo[mpz]   Tsukasa OI
• [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric   Tsukasa OI
• [PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric   Palmer Dabbelt
• [PATCH 1/6] RISC-V: Reorganize testcases for CFI directives   Nelson Chu
• [PATCH 2/2] ELF32: don't silently truncate relocation addends   Jan Beulich
• [PATCH 2/2] ELF32: don't silently truncate relocation addends   Alan Modra
• [PATCH 2/2] ELF32: don't silently truncate relocation addends   Jan Beulich
• [PATCH 2/2] x86-64: Use MAXPAGESIZE for the relro segment alignment   H.J. Lu
• [PATCH 2/2] x86-64: Use MAXPAGESIZE for the relro segment alignment   Michael Matz
• [PATCH 2/2] x86-64: Use MAXPAGESIZE for the relro segment alignment   H.J. Lu
• [PATCH 2/2] x86-64: Use MAXPAGESIZE for the relro segment alignment   Michael Matz
• [PATCH 2/3] opcodes/riscv: implement style support in the disassembler   Andrew Burgess
• [PATCH 2/3] opcodes/riscv: implement style support in the disassembler   Andrew Burgess
• [PATCH 2/3] RISC-V: Add 'Sscofpmf' extension with its CSRs   Tsukasa OI
• [PATCH 2/3] RISC-V: Stricter underscore handling for ISA   Tsukasa OI
• [PATCH 2/3] RISC-V: Stricter underscore handling for ISA   Nelson Chu
• [PATCH 2/3] RISC-V: Stricter underscore handling for ISA   Kito Cheng
• [PATCH 2/3] RISC-V: Stricter underscore handling for ISA   Andrew Waterman
• [PATCH 2/4] PR28824, relro security issues, x86 keep COMMONPAGESIZE relro   Alan Modra
• [PATCH 2/4] PR28824, relro security issues, x86 keep COMMONPAGESIZE relro   Alan Modra
• [PATCH 2/4] PR28824, relro security issues, x86 keep COMMONPAGESIZE relro   H.J. Lu
• [PATCH 2/4] RISC-V: Add disassembler tests for Zdinx regs   Tsukasa OI
• [PATCH 2/4] RISC-V: Add disassembler tests for Zdinx regs   Palmer Dabbelt
• [PATCH 2/5] RISC-V: Cache management instructions   Tsukasa OI
• [PATCH 2/5] RISC-V: Make indentation consistent   Tsukasa OI
• [PATCH 2/5] RISC-V: Make indentation consistent   Palmer Dabbelt
• [PATCH 2/6] RISC-V: Add Privileged Architecture 1.12 CSRs   Nelson Chu
• [PATCH 2/6] RISC-V: Add Privileged Architecture 1.12 CSRs   Tsukasa OI
• [PATCH 2/6] RISC-V: Add Privileged Architecture 1.12 CSRs   Nelson Chu
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Andrew Burgess
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Jan Beulich
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Andrew Burgess
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Jan Beulich
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Andrew Burgess
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Jan Beulich
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Andrew Burgess
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Jan Beulich
• [PATCH 3/3] opcodes/i386: partially implement disassembler style support   Andrew Burgess
• [PATCH 3/3] RISC-V: Add 'Sstc' extension and its CSRs   Tsukasa OI
• [PATCH 3/3] RISC-V: Tests for ISA string handling (underscore)   Tsukasa OI
• [PATCH 3/4] Remove bfd ELF_RELROPAGESIZE   Alan Modra
• [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs   Tsukasa OI
• [PATCH 3/4] RISC-V: Add assembler testcases for Zqinx regs   Palmer Dabbelt
• [PATCH 3/5] RISC-V: Cache management instruction testcases   Tsukasa OI
• [PATCH 3/5] RISC-V: Use different registers for testing   Tsukasa OI
• [PATCH 3/5] RISC-V: Use different registers for testing   Palmer Dabbelt
• [PATCH 3/6] RISC-V: Add Privileged Arch 1.12 CSR testcases   Nelson Chu
• [PATCH 4/4] Don't pass around expld.dataseg pointer   Alan Modra
• [PATCH 4/4] RISC-V: Add disassembler tests for Zqinx regs   Tsukasa OI
• [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set   Tsukasa OI
• [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set   Nelson Chu
• [PATCH 4/5] RISC-V: Prefetch hint instructions and operand set   Tsukasa OI
• [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements   Tsukasa OI
• [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements   Palmer Dabbelt
• [PATCH 4/5] RISC-V: Relax `fmv.[sdq]' requirements   Tsukasa OI
• [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs   Tsukasa OI
• [PATCH 5/5] RISC-V: Fix RV64_Zqinx to use register pairs   Palmer Dabbelt
• [PATCH 5/5] RISC-V: Prefetch hint instruction testcases   Tsukasa OI
• [PATCH] add missing extension info to 'invalid CSR' error   Nelson Chu
• [PATCH] add missing extension info to 'unrecognized opcode' error   Nelson Chu
• [PATCH] bfd: Remove return with expression in void function   Michael Forney
• [PATCH] bfd: Remove return with expression in void function   Nick Clifton
• [PATCH] bfd: Remove return with expression in void function   Michael Forney
• [PATCH] binutils/readelf: fix indentation in process_dynamic_section   Simon Marchi
• [PATCH] elf: Don't set VER_FLG_WEAK   Nick Clifton
• [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction.   Shaokun Zhang
• [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction.   Jan Beulich
• [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction.   Shaokun Zhang
• [PATCH] Fix the disassembly of the AArch64 SVE DECP/INCP/SQDECP/SQINCP instruction.   Jan Beulich
• [PATCH] gas/doc: Fix "a true results" typo   Richard Sandiford
• [PATCH] gas: retain whitespace between strings   Jan Beulich
• [PATCH] gold: Remove GNU ld incompatible --[no-]define-common [BZ #28871]   Fangrui Song
• [PATCH] gold: Remove GNU ld incompatible --[no-]define-common [BZ #28871]   Fāng-ruì Sòng
• [PATCH] i386: Allow GOT32 relocations against ABS symbols   H.J. Lu
• [PATCH] i386: Allow GOT32 relocations against ABS symbols   Jan Beulich
• [PATCH] i386: Allow GOT32 relocations against ABS symbols   H.J. Lu
• [PATCH] i386: Allow GOT32 relocations against ABS symbols   Jan Beulich
• [PATCH] i386: Allow GOT32 relocations against ABS symbols   H.J. Lu
• [PATCH] i386: Update I386_NEED_DYNAMIC_RELOC_TYPE_P for DT_TEXTREL   H.J. Lu
• [PATCH] i386: Update I386_NEED_DYNAMIC_RELOC_TYPE_P for DT_TEXTREL   H.J. Lu
• [PATCH] ld: Add a remove_1_page_gap_before_relro_segment option   H.J. Lu
• [PATCH] ld: Ad emultempl/emulation.em   H.J. Lu
• [PATCH] ld: Ad emultempl/emulation.em   H.J. Lu
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   H.J. Lu
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   H.J. Lu
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   Alan Modra
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   H.J. Lu
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   Alan Modra
• [PATCH] ld: Keep indirect symbol from IR if referenced from shared object   H.J. Lu
• [PATCH] ld: Remove emultempl/armcoff.em   H.J. Lu
• [PATCH] ld: Support customized output section type   Fangrui Song
• [PATCH] ld: Support customized output section type   Nick Clifton
• [PATCH] ld: Support customized output section type   Luca Boccassi
• [PATCH] ld: Support customized output section type   Fangrui Song
• [PATCH] ld: Support customized output section type   Luca Boccassi
• [PATCH] ld: Support customized output section type   Fangrui Song
• [PATCH] ld: Support customized output section type   Luca Boccassi
• [PATCH] ld: Support customized output section type   Fangrui Song
• [PATCH] ld: Support customized output section type   Michael Matz
• [PATCH] ld: Support customized output section type   Mike Frysinger
• [PATCH] libctf: delete unused libctf_TEXINFOS   Nick Alcock
• [PATCH] Load debug section only when dumping debug sections   Nick Clifton
• [PATCH] microblaze: fix fsqrt collicion to build on glibc-2.35   Sergei Trofimovich
• [PATCH] microblaze: fix fsqrt collicion to build on glibc-2.35   Nick Clifton
• [PATCH] RISC-V: correct FCVT.Q.L[U]   Jan Beulich
• [PATCH] RISC-V: Maintain a string to hold the canonical order   Kito Cheng
• [PATCH] RISC-V: Maintain a string to hold the canonical order   Tsukasa OI
• [PATCH] RISC-V: Maintain a string to hold the canonical order   Tsukasa OI
• [PATCH] RISC-V: Maintain a string to hold the canonical order   Kito Cheng
• [PATCH] RISC-V: make .insn actually work for 64-bit insns   Jan Beulich
• [PATCH] RISC-V: make .insn actually work for 64-bit insns   Nelson Chu
• [PATCH] RISC-V: Stop reporting warnings for mismatched extension versions   Palmer Dabbelt
• [PATCH] RISC-V: Stop reporting warnings for mismatched extension versions   Nelson Chu
• [PATCH] RISC-V: Stop reporting warnings for mismatched extension versions   Palmer Dabbelt
• [PATCH] RISC-V: Stop reporting warnings for mismatched extension versions   Nick Clifton
• [PATCH] RISC-V: Stop reporting warnings for mismatched extension versions   Palmer Dabbelt
• [PATCH] RISC-V: Update Zihintpause extension version   Andrew Waterman
• [PATCH] RISC-V: Update Zihintpause extension version   Tsukasa OI
• [PATCH] RISC-V: Update Zihintpause extension version   Palmer Dabbelt
• [PATCH] RISC-V: Update Zihintpause extension version   Tsukasa OI
• [PATCH] RISC-V: Update Zihintpause extension version   Hans-Peter Nilsson
• [PATCH] Support symbol+offset lookup in addr2line   Andi Kleen
• [PATCH] Support symbol+offset lookup in addr2line   H.J. Lu
• [patch] Update list of e_machine values   ccoutant@gmail.com
• [patch] Update list of e_machine values   H.J. Lu
• [patch] Update list of e_machine values   Cary Coutant
• [patch] Update list of e_machine values   H.J. Lu
• [patch] Update list of e_machine values   Fangrui Song
• [patch] Update list of e_machine values   Cary Coutant
• [PATCH] x86: Add has_sib to struct instr_info   H.J. Lu
• [PATCH] x86: Disallow invalid relocation against protected symbol   H.J. Lu
• [PATCH] x86: drop redundant x86-64-code16-2 test   Jan Beulich
• [PATCH] x86: Skip undefined symbol when finishing DT_RELR   H.J. Lu
• [PATCH] x86: Update X86_64_GOT_TYPE_P to cover more GOT relocations   H.J. Lu
• [PATCH RESEND] MIPS: make bnez, bnezl, beqz, and beqzl aliases   Sagar Patel
• [PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}   Shaokun Zhang
• [PATCH RESEND v2] Aarch64: Allow explicit size specifier for predicate operand of {sq, uq, }{incp, decp}   Jan Beulich
• [PATCH v1] binutils/doc: Document the RISC-V -M options   Palmer Dabbelt
• [PATCH v1] binutils/doc: Document the RISC-V -M options   Nelson Chu
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Philipp Tomsich
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Tsukasa OI
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Philipp Tomsich
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Hans-Peter Nilsson
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Palmer Dabbelt
• [PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)   Philipp Tomsich
• [PATCH v2 0/1] RISC-V: Fix RV32Q conflict   Tsukasa OI
• [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12   Jan Beulich
• [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12   Tsukasa OI
• [PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12   Tsukasa OI
• [PATCH v2 1/1] RISC-V: Fix RV32Q conflict   Tsukasa OI
• [PATCH v2 1/3] RISC-V: Enable elf attributes when default configure option isn't set.   Sebastian Huber
• [PATCH v2 2/5] RISC-V: Cache management instructions   Christoph Müllner
• [PATCH v2 2/5] RISC-V: Cache management instructions   Tsukasa OI
• [PATCH v2] ld: Add a remove_1_page_gap_before_relro_segment option   H.J. Lu
• [PATCH v2] libctf: Remove unused variable initialized to itself   Michael Forney
• [PATCH v2] RISC-V: Maintain a string to hold the canonical order   Kito Cheng
• [PATCH v2] RISC-V: Maintain a string to hold the canonical order   Nelson Chu
• [PATCH v2] RISC-V: Stop reporting warnings for mismatched extension versions   Palmer Dabbelt
• [PATCHv3 0/3] Add Type.is_scalar and Type.is_signed properties   Andrew Burgess
• [PATCHv3 0/3] Add Type.is_scalar and Type.is_signed properties   Andrew Burgess
• [PATCH v3 1/2] objcopy: Fix --only-keep-debug for ELF relocatables   Peilin Ye
• [PATCHv3 1/3] gdb/python: add Type.is_scalar property   Andrew Burgess
• [PATCH v3 2/2] binutils/testsuite: Test --only-keep-debug for ELF relocatables   Peilin Ye
• [PATCHv3 2/3] gdb/python: add Type.is_signed property   Andrew Burgess
• [PATCHv3 3/3] gdb/testsuite: add new test for comparing char types in Python   Andrew Burgess
• [PATCH v3] elf: Set p_align to the minimum page size if possible   Jan Beulich
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   Jan Beulich
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   jiawei@iscas.ac.cn
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   Philipp Tomsich
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   Jan Beulich
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   Tsukasa OI
• [PATCH v4 1/3] RISC-V: Minimal support of scalar crypto extension   Kito Cheng
• [PATCH v4] binutils/testsuite: Test --only-keep-debug on ELF relocatables   Peilin Ye
• [PATCH v4] binutils/testsuite: Test --only-keep-debug on ELF relocatables   Alan Modra
• [PATCH V4] gprofng: a new GNU profiler   Maciej W. Rozycki
• [PATCH V4] gprofng: a new GNU profiler   Jose E. Marchesi
• [PATCH V4] gprofng: a new GNU profiler   Vladimir Mezentsev
• [PATCH V4] gprofng: a new GNU profiler   Maciej W. Rozycki
• [PATCH V4] gprofng: a new GNU profiler   Jose E. Marchesi
• [RFC PATCH 0/2] gdb, opcodes: Add -M isa disassembler option to RISC-V   Tsukasa OI
• [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A   Tsukasa OI
• [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2A   Palmer Dabbelt
• [RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B   Tsukasa OI
• [RFC PATCH 1/2] gdb, opcodes: Add non-enum disassembler options   Tsukasa OI
• [RFC PATCH 1/2] RISC-V: Add floating point instruction metadata   Tsukasa OI
• [RFC PATCH 1/2] RISC-V: Prepare D/Q and Zdinx/Zqinx separation   Tsukasa OI
• [RFC PATCH 2/2] RISC-V: Add -M isa disassembler option   Tsukasa OI
• [RFC PATCH 2/2] RISC-V: Add -M isa disassembler option   Palmer Dabbelt
• [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs   Tsukasa OI
• [RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs   Tsukasa OI
• [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V   Tsukasa OI
• [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V   Nelson Chu
• [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V   Tsukasa OI
• [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V   Kito Cheng
• [RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V   Tsukasa OI
• [RFC PATCH v2 1/2] gdb, opcodes: Add non-enum disassembler options   Tsukasa OI
• [RFC PATCH v2 2/2] RISC-V: Add isa disassembler option   Tsukasa OI
• [RISCV] RISC-V GNU Toolchain Biweekly Sync-up call (Jan 27, 2022)   jiawei@iscas.ac.cn
• [RISCV] RISC-V GNU Toolchain Meeting Cancell (Feb 09, 2022)   jiawei@iscas.ac.cn
• Arm64: assembling adrp with operand involving .   Jan Beulich
• Arm64: assembling adrp with operand involving .   Nick Clifton
• Arm64: assembling adrp with operand involving .   Jan Beulich
• asan: buffer overflow in peXXigen.c   Alan Modra
• asan: buffer overflow in vms-alpha.c   Alan Modra
• asan : use of uninitialized value in buffer_and_nest   Alan Modra
• Coding style on bitfields usage and pointers to structures   Alan Modra
• Detect .eh_frame_hdr earlier for SIZEOF_HEADERS   Alan Modra
• elf: Check symbol version without any symbols   Alan Modra
• Enable "size" as a dumpprog in ld   Alan Modra
• gas local label and dollar label handling   Alan Modra
• GNU Binutils 2.38 has been released   Nick Clifton
• GNU Binutils 2.38 has been released   Waldemar Brodkorb
• GNU Binutils 2.38 has been released   Jan Beulich
• GNU Binutils 2.38 has been released   Waldemar Brodkorb
• GNU Binutils 2.38 has been released   Jan Beulich
• GNU Binutils 2.38 has been released   Waldemar Brodkorb
• GNU Binutils 2.38 has been released   Jim Wilson
• GNU Binutils 2.38 has been released   Jim Wilson
• gprofng: update file texinfo.tex?   Ruud van der Pas
• gprofng: update file texinfo.tex?   Nick Clifton
• gprofng: update file texinfo.tex?   Ruud van der Pas
• New French PO file for 'gold' (version 2.37.90)   Translation Project Robot
• New French PO file for 'ld' (version 2.37.90)   Translation Project Robot
• New Romanian PO file for 'gprof' (version 2.36.90)   Translation Project Robot
• New Serbian PO file for 'bfd' (version 2.37.90)   Translation Project Robot
• New Serbian PO file for 'bfd' (version 2.37.90)   Nick Clifton
• New Serbian PO file for 'binutils' (version 2.37.90)   Translation Project Robot
• New Serbian PO file for 'gold' (version 2.37.90)   Translation Project Robot
• New Serbian PO file for 'ld' (version 2.37.90)   Translation Project Robot
• New Serbian PO file for 'opcodes' (version 2.37.90)   Translation Project Robot
• Noted slowness in profile loading with binutils 2.37   Alexander Lindsay
• Noted slowness in profile loading with binutils 2.37   H.J. Lu
• Noted slowness in profile loading with binutils 2.37   Alexander Lindsay
• Noted slowness in profile loading with binutils 2.37   Alan Modra
• Noted slowness in profile loading with binutils 2.37   Nick Clifton
• Noted slowness in profile loading with binutils 2.37   Alexander Lindsay
• Noted slowness in profile loading with binutils 2.37   Alexander Lindsay
• Noted slowness in profile loading with binutils 2.37   Nick Clifton
• Output section type (READONLY)   Fangrui Song
• Output section type (READONLY)   Nick Clifton
• Output section type (READONLY)   Luca Boccassi
• Output section type (READONLY)   Fangrui Song
• Output section type (READONLY)   Michael Matz
• Output section type (READONLY)   Luca Boccassi
• Output section type (READONLY)   Nick Clifton
• Output section type (READONLY)   Luca Boccassi
• Output section type (READONLY)   Fangrui Song
• Output section type (READONLY)   Alan Modra
• Output section type (READONLY)   Fangrui Song
• pe_ILF_make_a_symbol_reloc segfault   Alan Modra
• PowerPC64 treatment of absolute symbols   Alan Modra
• PR28763, SIGSEGV during processing of program headers via readelf   Alan Modra
• PR28827 - [2.38 Regression] ld hits assertion building LLVM 9 on powerpc64le-linux-gnu   Alan Modra
• PR28827 - [2.38 Regression] ld hits assertion building LLVM 9 on powerpc64le-linux-gnu   H.J. Lu
• PR28827 testcase   Alan Modra
• PR28827 testcase   Fangrui Song
• PR28827 testcase   Alan Modra
• PR28827 testcase   Nick Clifton
• PR28827 testcase   Alan Modra
• PR28827 testcase   H.J. Lu
• PR28827 testcase   Alan Modra
• PR28827 testcase   H.J. Lu
• PR28827 testcase   Alan Modra
• PR28827 testcase   H.J. Lu
• PR28827 testcase   Alan Modra
• PR28827 testcase   Nick Clifton
• PR28827 testcase   H.J. Lu
• PR28827 testcase   Alan Modra
• PR28862, heap-buffer-overflow in parse_stab_string   Alan Modra
• PR28882, build failure with gcc-4.2 due to use of 0b literals   Alan Modra
• regression with binutils 2.28 for ppc   Waldemar Brodkorb
• regression with binutils 2.28 for ppc   Peter Bergner
• regression with binutils 2.28 for ppc   Peter Bergner
• regression with binutils 2.28 for ppc   Waldemar Brodkorb
• regression with binutils 2.28 for ppc   Peter Bergner
• regression with binutils 2.28 for ppc   Alan Modra
• regression with binutils 2.28 for ppc   Peter Bergner
• regression with binutils 2.28 for ppc   Alan Modra
• regression with binutils 2.28 for ppc   Alan Modra
• regression with binutils 2.28 for ppc   Waldemar Brodkorb
• RISC-V: mapping symbols vs "unimpl"   Jan Beulich
• RISC-V: mapping symbols vs "unimpl"   Andrew Waterman
• RISC-V: mapping symbols vs "unimpl"   Nelson Chu
• RISC-V: mapping symbols vs "unimpl"   Jan Beulich
• RISC-V: observations / questions   Jan Beulich
• RISC-V: observations / questions   Andrew Waterman
• The 2.38 branch has been created.   Palmer Dabbelt
• The 2.38 branch has been created.   Nick Clifton
• The 2.38 branch has been created.   Fangrui Song
• The 2.38 branch has been created.   Nick Clifton
• The 2.38 branch has been created.   Fangrui Song
• The 2.38 branch is open for normal commits   Nick Clifton
• ubsan: s_app_line integer overflow   Alan Modra
• What to do when sh_addralign isn't a power of two   Alan Modra
• Work around gcc-4 warnings in elf64-ppc.c   Alan Modra
• x86-64: new CET-enabled PLT format proposal   Rui Ueyama
• x86-64: new CET-enabled PLT format proposal   H.J. Lu
• x86-64: new CET-enabled PLT format proposal   Rui Ueyama
• your patch "RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR"   Jan Beulich
• your patch "RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR"   Nelson Chu
• your patch "RISC-V: Add PT_RISCV_ATTRIBUTES and add it to PHDR"   Jan Beulich

Last message date: Mon Feb 28 15:54:30 GMT 2022
Archived on: Mon Feb 28 15:54:35 GMT 2022

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