[PATCH 1/5] RISC-V: Fix disassembling Zfinx with -M numeric
Tsukasa OI
research_trasio@irq.a4lg.com
Tue Feb 1 13:49:02 GMT 2022
This commit fixes floating point operand register names from ABI ones
to dynamically set ones.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
Zfinx extension and -M numeric disassembler option.
* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
names to disassemble Zfinx instructions.
---
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 ++++++++++
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 ++
opcodes/riscv-dis.c | 2 +-
3 files changed, 13 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.d b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
new file mode 100644
index 00000000000..ba3f62295eb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.d
@@ -0,0 +1,10 @@
+#as: -march=rv64ima_zfinx
+#source: zfinx-dis-numeric.s
+#objdump: -dr -Mnumeric
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+x10,x11,x12
diff --git a/gas/testsuite/gas/riscv/zfinx-dis-numeric.s b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
new file mode 100644
index 00000000000..b55cbd56b21
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfinx-dis-numeric.s
@@ -0,0 +1,2 @@
+target:
+ feq.s a0, a1, a2
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 34724d4aec5..07de1ce080a 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -605,7 +605,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
/* If arch has ZFINX flags, use gpr for disassemble. */
if(riscv_subset_supports (&riscv_rps_dis, "zfinx"))
- riscv_fpr_names = riscv_gpr_names_abi;
+ riscv_fpr_names = riscv_gpr_names;
for (; op->name; op++)
{
--
2.32.0
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