[PATCH] RISC-V: Update Zihintpause extension version

[Andrew Waterman]

On Mon, Jan 31, 2022 at 8:45 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sun, 30 Jan 2022 03:37:41 PST (-0800), binutils@sourceware.org wrote:
> > Because ratified Zihintpause extension has a version number of 2.0
> > (not 1.0), we should update the number.
>
> The ISA manual also says it's ratified so having it in the draft set is
> kind of odd, but I'm not sure which spec version it should be included
> in.  The commits saying it was ratified are in August 2021, but I can't
> find a spec version that's listed as ratified and contains the new 2.0
> (there was also an earlier 2.0, from before the 1.0).
>
> Not sure if this matters, though.  Looks like the only non-commentary
> differents are: from the original 2.0 to 1.0, the text "No architectural
> state is changed." was added; and from 1.0 to 2.0 the text "{\em fm}=0,
> {\em rd}={\tt x0}, and {\em rs1}={\tt x0}" was added (to the encoding
> section).  The second one isn't substantive, and while the first one
> reads like a change to me IIRC we've been through that before and I just
> have the definition of architectural state change wrong.

The first one isn't substantive, either, because of the definition of
HINT.  It's just a clarification.

>
> >
> > bfd/ChangeLog:
> >
> >       * elfxx-riscv.c (riscv_supported_std_z_ext): Update version
> >       number of Zihintpause extension.
> > ---
> >  bfd/elfxx-riscv.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> > index 9f52bb545ac..29755a6cb0a 100644
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1183,7 +1183,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
> >    {"zicsr",          ISA_SPEC_CLASS_20190608,        2, 0,  0 },
> >    {"zifencei",               ISA_SPEC_CLASS_20191213,        2, 0,  0 },
> >    {"zifencei",               ISA_SPEC_CLASS_20190608,        2, 0,  0 },
> > -  {"zihintpause",    ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> > +  {"zihintpause",    ISA_SPEC_CLASS_DRAFT,           2, 0,  0 },
> >    {"zfinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> >    {"zdinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> >    {"zqinx",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
> >
> > base-commit: 35b5767cf47169d11aa059fce0ed5b0fc213045d