RISC-V: observations / questions

[Jan Beulich]

Hello,

besides the two relatively simple patches that I have sent earlier
today, I do have a few more questions:

1) Many insn encodings using x0 as the destination are marked as hint
encodings. Wouldn't things like "add x0, x1, x2" therefore better be
at least warned about?

2) Insns like "beq x0, x0, ." (perhaps not very useful outside of
assembler / disassembler test suites) result in odd ".L0 " labels in
the object's symbol table. My best guess so far was that this may be
a result of "#define tc_fix_adjustable(fixp) 0". As these labels are
somewhat confusing - would there be a way to suppress their emission?

3) When the assembler can determine a branch's destination, e.g. in
"beq x0, x0, .+1", wouldn't it be useful to warn about the non-even
destination address? And with the C extension disabled even about
any one not evenly divisible by 4?

4) A number of CSRs are valid in RV32 mode only. Shouldn't their use
be diagnosed when assembling 64-bit code? (I thought I had seen a
patch to this effect, but not overly old gas still happily accepts
them.)

5) While possibly not too interesting for RV32, in RV64 auipc and
lui have immediate operands which are sign-extended. Yet gas chokes
on any of

	auipc	x31, -0x100
	lui	x31, -0x100
	c.lui	x31, -0x20

Shouldn't signed operands be permitted (if not required) there, and
then ideally permitted (but not required) also on RV32?

Thanks for any helpful insight,
Jan