[RFC PATCH v2 0/2] gdb, opcodes: Add isa disassembler option to RISC-V
Tsukasa OI
research_trasio@irq.a4lg.com
Sun Feb 6 02:10:35 GMT 2022
*** NOTE ***
PATCH 1 contains non-RISC-V (GDB-related) changes.
This patchset adds support for isa=ISA diassembler option to RISC-V.
- objdump: -M isa=rv[32|64]...
- gdb: set disassembler-options isa=rv[32|64]...
This patchset is version 2. Version 1 is here:
<https://sourceware.org/pipermail/binutils/2022-February/119639.html>
<https://github.com/a4lg/binutils-gdb/tree/a4lg/snapshots/2022-02-05/riscv-dis-isa>
My development branch on GitHub:
<https://github.com/a4lg/binutils-gdb/tree/riscv-dis-isa>
[Changes between RFC PATCH v1 and RFC PATCH v2]
The only functional change in the RFC PATCH v2 is that we reset `xlen'
variable to `0' before parsing ISA string. It has no effect on objdump
but on GDB, it stops preserving last XLEN value before setting invalid
ISA string (not starting with "rv32" or "rv64").
Rest of the changes are editorial. My language got broken while writing
v1 but I think most of them are fixed in v2. Also, most "-M isa"
(objdump-only) references are replaced with just "isa" to indicate
both objdump and GDB options.
Renamed `xlen_set_by_option' to `xlen_by_isa' for clarity (meaning XLEN
set by "ISA string" option).
Tsukasa OI (2):
gdb, opcodes: Add non-enum disassembler options
RISC-V: Add isa disassembler option
gdb/disasm.c | 4 ++++
include/dis-asm.h | 3 ++-
opcodes/arc-dis.c | 2 ++
opcodes/mips-dis.c | 2 ++
opcodes/riscv-dis.c | 35 ++++++++++++++++++++++++++++-------
5 files changed, 38 insertions(+), 8 deletions(-)
base-commit: 94e57f287f96af6af97dd086e4a04ddf55b7cf60
--
2.32.0
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