[PATCH v1] RISC-V: Add mtinst and mtval2 CSRs (defined in priv-spec 1.12)

[Philipp Tomsich]

Tsukasa,

Last time I heard, you did not have copyright assignments in place.
Until this is resolved, I can not look at your patches to not lose the
ability to independently develop if needed (our community has been
burnt in this regard before).

It feels like our entire community fell short on the current 2.38
release, as we are missing support for some of the Priv 1.12 (i.e.,
Ss1-12 and Sm1-12, as the official nomenclature for these extensions
is) content.   Given that Priv 1.12 was ratified last year, it is pity
that it will not be contained in a full release for another half year.
I created and sent this patch in response to an issue reported by a DV
team — this is a strong reminder that every time upstream enablement
lags behind, many members of the RISC-V ecosystem will be tracking
issues and spend time on maintaining forks.

On Fri, 4 Feb 2022 at 05:15, Tsukasa OI <research_trasio@irq.a4lg.com> wrote:
>
> I submitted similar changes in a larger patchset.  If the review of mine
> takes too much time, it would be good to apply yours first.
>
> Also, it would be always happy to see that we solve the same problem the
> same way (the only difference between ours I see is letter casing).

With the addition of opcodes and CSRs, there's really only one way to
do it (except for insignificant changes).
So, I'm glad that there's no significant difference: I'll chalk that
up as a passed review ;-)

Thanks,
Philipp.