[PATCH 4/4] RISC-V: Add disassembler tests for Zqinx regs

[Tsukasa OI]

This commid adds disassembler tests for invalid Zqinx register numbers
(make sure that we don't disassemble invalid encodings).

gas/ChangeLog:

	* testsuite/gas/riscv/zqinx-32-regpair-dis.s: New test to make
	sure that invalid encodings are not disassembled.
	* testsuite/gas/riscv/zqinx-32-regpair-dis.d: Likewise.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.s: New test to make
	sure that invalid encoding is not disassembled.
	* testsuite/gas/riscv/zqinx-64-regpair-dis.d: Likewise.
---
 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s |  7 +++++++
 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d | 11 +++++++++++
 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s |  5 +++++
 4 files changed, 35 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
 create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
 create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
 create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s

diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
new file mode 100644
index 00000000000..5af92477116
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
@@ -0,0 +1,12 @@
+#as: -march=rv32ima_zqinx
+#source: zqinx-32-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06c47253[ 	]+fadd.q[ 	]+x4,x8,x12
+[ 	]+[0-9a-f]+:[ 	]+06d4f2d3[ 	]+\.4byte[ 	]+0x6d4f2d3
+[ 	]+[0-9a-f]+:[ 	]+06e57353[ 	]+\.4byte[ 	]+0x6e57353
diff --git a/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
new file mode 100644
index 00000000000..e11e671ecdc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
@@ -0,0 +1,7 @@
+target:
+	# fadd.q x4, x8, x12
+	.insn	0x06c47253
+	# fadd.q x5, x9, x13 (invalid)
+	.insn	0x06d4f2d3
+	# fadd.q x6, x10, x14 (invalid)
+	.insn	0x06e57353
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
new file mode 100644
index 00000000000..894ed34948e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
@@ -0,0 +1,11 @@
+#as: -march=rv64ima_zqinx
+#source: zqinx-64-regpair-dis.s
+#objdump: -dr -Mnumeric
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+06627153[ 	]+fadd.q[ 	]+x2,x4,x6
+[ 	]+[0-9a-f]+:[ 	]+0672f1d3[ 	]+\.4byte[ 	]+0x672f1d3
diff --git a/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
new file mode 100644
index 00000000000..9edeae84ba7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
@@ -0,0 +1,5 @@
+target:
+	# fadd.q x2, x4, x6
+	.insn	0x06627153
+	# fadd.q x3, x5, x7 (invalid)
+	.insn	0x0672f1d3
-- 
2.32.0