[RFC PATCH 0/2] RISC-V: Zfinx fixes/enhancements: Part 2B

[Tsukasa OI]

[About this patchset]

This is the Part 2B (part 2 option B) of my Z[fdq]inx fixes and
enhancements.  See Part 1 for general background and Part 2A for the
issue this patchset tries to fix.

<https://sourceware.org/pipermail/binutils/2022-February/119570.html> (Part 1)
<https://sourceware.org/pipermail/binutils/2022-February/119576.html> (Part 2A)




Tsukasa OI (2):
  RISC-V: Add floating point instruction metadata
  RISC-V: Validate Zdinx/Zqinx register pairs

 gas/config/tc-riscv.c  |  65 ++++-
 include/opcode/riscv.h |  19 ++
 opcodes/riscv-opc.c    | 522 ++++++++++++++++++++---------------------
 3 files changed, 339 insertions(+), 267 deletions(-)


base-commit: e327c35ef5768789d3ba41a629f178f5eec32790
prerequisite-patch-id: 9e408f2e6186c8956aae077daf95f38b9ad98675
prerequisite-patch-id: 32ea143f7662a3297a7cf809cec6454e788f2916
prerequisite-patch-id: 25d5aa65f72b1b4f1f52c92aa0f8ac30d218cc9c
prerequisite-patch-id: 6599ccdcc15585db285c30e14528f905327fd638
prerequisite-patch-id: a5f3689afda87a68d4faae698c438aa3211521e0
-- 
2.32.0