[PATCH v2 0/3] RISC-V: Prepare Privileged Architecture 1.12

Tsukasa OI research_trasio@irq.a4lg.com
Mon Feb 21 13:49:05 GMT 2022


Ah, I forgot to note.

The original Privileged Architecture 1.12 patchsets:
<https://sourceware.org/pipermail/binutils/2021-December/119004.html> (v1)
<https://sourceware.org/pipermail/binutils/2021-December/119008.html> (v2)

are superseded by the latest one:
<https://sourceware.org/pipermail/binutils/2022-January/119282.html> (CSR only v1)

... as Privileged Architecture 1.12 itself is implemented as a part of
hypervisor support (this is merged into master):
<https://sourceware.org/pipermail/binutils/2021-December/118980.html>

Thanks,
Tsukasa

On 2022/02/21 22:38, Tsukasa OI via Binutils wrote:
> On 2022/02/21 22:21, Jan Beulich wrote:
>> On 24.12.2021 04:22, Tsukasa OI via Binutils wrote:
>>> Tsukasa OI (3):
>>>   RISC-V: Make testcase indentation consistent
>>>   RISC-V: Unify "access all CSRs" testcases
>>>   RISC-V: Add Privileged Architecture version 1.12
>>>
>>>  bfd/cpu-riscv.c                               |   1 +
>>>  bfd/cpu-riscv.h                               |   1 +
>>>  gas/config/tc-riscv.c                         |   2 +-
>>>  gas/testsuite/gas/riscv/csr-dw-regnums.d      |   2 +-
>>>  gas/testsuite/gas/riscv/option-arch-01a.d     |   8 +-
>>>  gas/testsuite/gas/riscv/priv-reg-access-all.s | 292 ++++++++++
>>>  gas/testsuite/gas/riscv/priv-reg-fail-fext.d  |   2 +-
>>>  .../gas/riscv/priv-reg-fail-read-only-01.d    |   2 +-
>>>  .../gas/riscv/priv-reg-fail-read-only-01.s    | 267 +--------
>>>  .../gas/riscv/priv-reg-fail-read-only-02.d    |   2 +-
>>>  .../gas/riscv/priv-reg-fail-rv32-only.d       |   2 +-
>>>  .../gas/riscv/priv-reg-fail-version-1p10.d    |   2 +-
>>>  .../gas/riscv/priv-reg-fail-version-1p11.d    |   2 +-
>>>  .../gas/riscv/priv-reg-fail-version-1p12.d    |  11 +
>>>  .../gas/riscv/priv-reg-fail-version-1p12.l    |  24 +
>>>  .../gas/riscv/priv-reg-fail-version-1p9p1.d   |   2 +-
>>>  gas/testsuite/gas/riscv/priv-reg-fail-zkr.d   |   2 +-
>>>  .../gas/riscv/priv-reg-version-1p10.d         | 534 +++++++++---------
>>>  .../gas/riscv/priv-reg-version-1p11.d         | 534 +++++++++---------
>>>  .../gas/riscv/priv-reg-version-1p12.d         | 275 +++++++++
>>
>> Comparing with the spec I find SCONTEXT still is numbered 0x7aa in here,
>> when the doc says 0x5a8. Was this overlooked? Or is the doc wrong?
>>
>> Jan
> 
> You pointed out that right but still, this is intentional.
> 
> In PATCH 3/6 commit message, I wrote:
>> (except moved "scontext" and
>> new "mscontext").
> 
> Because `scontext' is a part of debug specification (NOT privileged
> specification), I thought it should be controlled by debug specification
> version option like one proposed by Nelson Chu:
> 
> <https://sourceware.org/pipermail/binutils/2021-August/117568.html>
> 
> Note that debug specification 1.0 (with moved `scontext' and new
> `mscontext') is not ratified yet.
> 
> <https://github.com/riscv/riscv-debug-spec/commit/b659d7dc7f578e1a2a76f9e62a5eec0f2d80045c>
> 
> Tsukasa
> 
>>
>>>  .../gas/riscv/priv-reg-version-1p9p1.d        | 534 +++++++++---------
>>>  gas/testsuite/gas/riscv/priv-reg.s            | 294 +---------
>>>  22 files changed, 1421 insertions(+), 1374 deletions(-)
>>>  create mode 100644 gas/testsuite/gas/riscv/priv-reg-access-all.s
>>>  create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.d
>>>  create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p12.l
>>>  create mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p12.d
>>>
>>>
>>> base-commit: d20236e748ab70e9243960850eef64838f1b9721
>>
> 


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