[RFC PATCH 2/2] RISC-V: Validate Zdinx/Zqinx register pairs

[Tsukasa OI]

This commit adds floating point register validation on Zdinx/Zqinx
extensions enabled.  Assembler only.

gas/ChangeLog:

	* config/tc-riscv.c (reg_lookup_fp): New function to look up and
	validate floating point register operands.
	(riscv_ip): Use `reg_lookup_fp' to look up FPRs.
---
 gas/config/tc-riscv.c | 65 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 59 insertions(+), 6 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 25908597436..bfb2f94b061 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2137,6 +2137,61 @@ riscv_handle_implicit_zero_offset (expressionS *ep, const char *s)
   return false;
 }
 
+/* Look up floating point register and validate against operand type.
+   This function checks invalid register such as "x1" on a FP64 operand
+   in RV32_Zdinx.  */
+
+static bool
+reg_lookup_fp (char operand, char **str,
+	      struct riscv_opcode *insn, unsigned int *regno)
+{
+  bool is_zfinx = riscv_subset_supports (&riscv_rps_as, "zfinx");
+  unsigned int float_size = insn->pinfo & INSN_FLOAT;
+  if (!reg_lookup (str, (is_zfinx ? RCLASS_GPR : RCLASS_FPR), regno))
+    return false;
+  if (!is_zfinx || (insn->pinfo & INSN_FLOAT_VAR))
+    return true;
+  /* Source operand for fcvt.[FLOAT].[FLOAT] instructions requires
+     different float_size than the destination.  */
+  if ((insn->pinfo & INSN_FCVT_F_F) && operand == 'S')
+    float_size = (insn->pinfo & INSN_FCVT_SRC) >> INSN_FCVT_SRC_SHIFT;
+  /* Check register index for Zdinx/Zqinx.  */
+  switch (float_size)
+    {
+    case INSN_FLOAT_S:
+      return true;
+    case INSN_FLOAT_D:
+      switch (xlen)
+	{
+	case 32:
+	  if (*regno & 0x01)
+	    break;
+	  return true;
+	default:
+	  return true;
+	}
+      break;
+    case INSN_FLOAT_Q:
+      switch (xlen)
+	{
+	case 32:
+	  if (*regno & 0x03)
+	    break;
+	  return true;
+	case 64:
+	  if (*regno & 0x01)
+	    break;
+	  return true;
+	default:
+	  return true;
+	}
+      break;
+    default:
+      return false;
+    }
+  return false;
+}
+
 /* All RISC-V CSR instructions belong to one of these classes.  */
 enum csr_insn_type
 {
@@ -2518,19 +2573,19 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		case 'a':
 		  goto jump;
 		case 'S': /* Floating-point RS1 x8-x15.  */
-		  if (!reg_lookup (&asarg, RCLASS_FPR, &regno)
+		  if (!reg_lookup_fp(*oparg, &asarg, insn, &regno)
 		      || !(regno >= 8 && regno <= 15))
 		    break;
 		  INSERT_OPERAND (CRS1S, *ip, regno % 8);
 		  continue;
 		case 'D': /* Floating-point RS2 x8-x15.  */
-		  if (!reg_lookup (&asarg, RCLASS_FPR, &regno)
+		  if (!reg_lookup_fp(*oparg, &asarg, insn, &regno)
 		      || !(regno >= 8 && regno <= 15))
 		    break;
 		  INSERT_OPERAND (CRS2S, *ip, regno % 8);
 		  continue;
 		case 'T': /* Floating-point RS2.  */
-		  if (!reg_lookup (&asarg, RCLASS_FPR, &regno))
+		  if (!reg_lookup_fp(*oparg, &asarg, insn, &regno))
 		    break;
 		  INSERT_OPERAND (CRS2, *ip, regno);
 		  continue;
@@ -2897,9 +2952,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	    case 'T': /* Floating point RS2.  */
 	    case 'U': /* Floating point RS1 and RS2.  */
 	    case 'R': /* Floating point RS3.  */
-	      if (reg_lookup (&asarg,
-			      (riscv_subset_supports (&riscv_rps_as, "zfinx")
-			      ? RCLASS_GPR : RCLASS_FPR), &regno))
+	      if (reg_lookup_fp(*oparg, &asarg, insn, &regno))
 		{
 		  char c = *oparg;
 		  if (*asarg == ' ')
-- 
2.32.0