This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
RE: [PATCH 2/4] Arm64: correct uzp{1,2} mnemonics
- From: Tamar Christina <Tamar dot Christina at arm dot com>
- To: Jan Beulich <JBeulich at suse dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Mihail Ionescu <Mihail dot Ionescu at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, nd <nd at arm dot com>
- Date: Mon, 30 Dec 2019 11:40:50 +0000
- Subject: RE: [PATCH 2/4] Arm64: correct uzp{1,2} mnemonics
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6cbM7QMyrR62w6v+ONofXJKX6t+41w5x6iTa/Zn1J40=; b=QfWr8jB22xPby1BjSUUGBZQ/u5NbyRwZJ+n37QCVnNUiuOn3QsQrIzc9KLAbKA8QO/3Z8zHolXMbrRBhDAE4sgPTSMhIM1AToQEO38+rH8VUiV+6hiTzQsI+kiiBY0Hm6E1gG1urSgSc1NdxsV2Lqw+r4/N3LCKDYgROVIRUMJp+FUcAQ7RnACAgas4Q6zUA3DkFo4064M7l9JxSFn1aEdEHPNIXR4PsrGuk0P/Gnaz+kzJpCcdc7HHl1uffy8tkClMDJMAlxH8uyNEnRsNCKettbBV62/aQB7g6s72TIytCRosx2wxUZaGLnMGvPViVXNnc9a9P2JLt9PIJPlMLiA==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bfzwGTKN374AyuQ83MZR6Bk2uZldkbqPyQFQRATOxBGQjopFa43SsroC1lQE9QSEuUN8V52iBLi/sNNwVyTMAlKf8l0vnQ3hC4UqIAW1JCaqaR3BVEPVoWcvrYo6jXhgOG0kP/aPVn4c3aw+HBTmiqXhWOrwIo4R1aEmz2zIHrHL7P+Ni2d2pVowRMjOpeH34vrbn23HfW3G2ZDQYp18KQP/TpvPO4p4meTJCb5w4GWFTBp0lrGwIbRQ6scv+WilbcgRn8JKSlsCiP7phDA6cGhqr+oZV8yaHMrm7/WeXPeQKGyEJnarHPRGQ5rOUxXlEaEg9Vh23u++/WwqH7NHrw==
- Original-authentication-results: spf=none (sender IP is ) smtp.mailfrom=Tamar dot Christina at arm dot com;
- References: <37213fea-ae2e-0293-a042-9db2274cd061@suse.com> <c3c081b2-b21d-5f24-c5bb-ac7c074e1639@suse.com>
Hi Jan,
I'm not a maintainer so you still need approval but this fix is correct.
Thanks!,
Tamar
> -----Original Message-----
> From: binutils-owner@sourceware.org <binutils-owner@sourceware.org>
> On Behalf Of Jan Beulich
> Sent: Friday, December 27, 2019 10:40
> To: binutils@sourceware.org
> Cc: Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Mihail Ionescu
> <Mihail.Ionescu@arm.com>; Richard Earnshaw
> <Richard.Earnshaw@arm.com>
> Subject: [PATCH 2/4] Arm64: correct uzp{1,2} mnemonics
>
> According to the specification, and in line with the pre-existing predicate
> forms, the mnemonics do not include an 'i'.
>
> gas/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
> * testsuite/gas/aarch64/f64mm.d: Adjust expectations.
>
> opcodes/
> 2020-01-XX Jan Beulich <jbeulich@suse.com>
>
> * opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
> uzip{1,2}.
> * opcodes/aarch64-dis-2.c: Re-generate.
>
> --- a/gas/testsuite/gas/aarch64/f64mm.d
> +++ b/gas/testsuite/gas/aarch64/f64mm.d
> @@ -52,10 +52,10 @@ Disassembly of section \.text:
> *[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q
> *[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q
> *[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q
> - *[0-9a-f]+: 05a50ab1 uzip1 z17\.q, z21\.q, z5\.q
> - *[0-9a-f]+: 05a00800 uzip1 z0\.q, z0\.q, z0\.q
> - *[0-9a-f]+: 05a50eb1 uzip2 z17\.q, z21\.q, z5\.q
> - *[0-9a-f]+: 05a00c00 uzip2 z0\.q, z0\.q, z0\.q
> + *[0-9a-f]+: 05a50ab1 uzp1 z17\.q, z21\.q, z5\.q
> + *[0-9a-f]+: 05a00800 uzp1 z0\.q, z0\.q, z0\.q
> + *[0-9a-f]+: 05a50eb1 uzp2 z17\.q, z21\.q, z5\.q
> + *[0-9a-f]+: 05a00c00 uzp2 z0\.q, z0\.q, z0\.q
> *[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q
> *[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q
> *[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q
> --- a/gas/testsuite/gas/aarch64/f64mm.s
> +++ b/gas/testsuite/gas/aarch64/f64mm.s
> @@ -60,10 +60,10 @@ zip1 z0.q, z0.q, z0.q
> zip2 z17.q, z21.q, z5.q
> zip2 z0.q, z0.q, z0.q
>
> -uzip1 z17.q, z21.q, z5.q
> -uzip1 z0.q, z0.q, z0.q
> -uzip2 z17.q, z21.q, z5.q
> -uzip2 z0.q, z0.q, z0.q
> +uzp1 z17.q, z21.q, z5.q
> +uzp1 z0.q, z0.q, z0.q
> +uzp2 z17.q, z21.q, z5.q
> +uzp2 z0.q, z0.q, z0.q
>
> trn1 z17.q, z21.q, z5.q
> trn1 z0.q, z0.q, z0.q
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -5084,8 +5084,8 @@ struct aarch64_opcode aarch64_opcode_tab
> F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3
> (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
> F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> - F64MATMUL_SVE_INSN ("uzip1", 0x05a00800, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> - F64MATMUL_SVE_INSN ("uzip2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> + F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> + F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3
> (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
> /* Matrix Multiply advanced SIMD instructions. */