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[PATCH 2/4] Arm64: correct uzp{1,2} mnemonics
- From: Jan Beulich <JBeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Mihail Ionescu <mihail dot ionescu at arm dot com>, Richard Earnshaw <rearnsha at arm dot com>
- Date: Fri, 27 Dec 2019 10:39:38 +0000
- Subject: [PATCH 2/4] Arm64: correct uzp{1,2} mnemonics
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- References: <37213fea-ae2e-0293-a042-9db2274cd061@suse.com>
According to the specification, and in line with the pre-existing
predicate forms, the mnemonics do not include an 'i'.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.s: Drop 'i' from uzip<n>.
* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
uzip{1,2}.
* opcodes/aarch64-dis-2.c: Re-generate.
--- a/gas/testsuite/gas/aarch64/f64mm.d
+++ b/gas/testsuite/gas/aarch64/f64mm.d
@@ -52,10 +52,10 @@ Disassembly of section \.text:
*[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q
- *[0-9a-f]+: 05a50ab1 uzip1 z17\.q, z21\.q, z5\.q
- *[0-9a-f]+: 05a00800 uzip1 z0\.q, z0\.q, z0\.q
- *[0-9a-f]+: 05a50eb1 uzip2 z17\.q, z21\.q, z5\.q
- *[0-9a-f]+: 05a00c00 uzip2 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a50ab1 uzp1 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00800 uzp1 z0\.q, z0\.q, z0\.q
+ *[0-9a-f]+: 05a50eb1 uzp2 z17\.q, z21\.q, z5\.q
+ *[0-9a-f]+: 05a00c00 uzp2 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q
*[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q
*[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q
--- a/gas/testsuite/gas/aarch64/f64mm.s
+++ b/gas/testsuite/gas/aarch64/f64mm.s
@@ -60,10 +60,10 @@ zip1 z0.q, z0.q, z0.q
zip2 z17.q, z21.q, z5.q
zip2 z0.q, z0.q, z0.q
-uzip1 z17.q, z21.q, z5.q
-uzip1 z0.q, z0.q, z0.q
-uzip2 z17.q, z21.q, z5.q
-uzip2 z0.q, z0.q, z0.q
+uzp1 z17.q, z21.q, z5.q
+uzp1 z0.q, z0.q, z0.q
+uzp2 z17.q, z21.q, z5.q
+uzp2 z0.q, z0.q, z0.q
trn1 z17.q, z21.q, z5.q
trn1 z0.q, z0.q, z0.q
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5084,8 +5084,8 @@ struct aarch64_opcode aarch64_opcode_tab
F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
- F64MATMUL_SVE_INSN ("uzip1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
- F64MATMUL_SVE_INSN ("uzip2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
+ F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
/* Matrix Multiply advanced SIMD instructions. */