This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH 1/4] Arm64: correct 64-bit element fmmla encoding
- From: Jan Beulich <JBeulich at suse dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Mihail Ionescu <mihail dot ionescu at arm dot com>, Richard Earnshaw <rearnsha at arm dot com>
- Date: Fri, 27 Dec 2019 10:38:52 +0000
- Subject: [PATCH 1/4] Arm64: correct 64-bit element fmmla encoding
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AA9mZUXQiTbar7LnT/MRs9Itr59G2vB/VKjM8NrcUJQ=; b=mH9Qi7N23r/a4EwpFP/7/NcwWX7/2WXemW4UFbIsvz3zhXLsdwiMbFjuFxo+iKV+EWenG/8HevKKefsvAbHpY0SJlM7xwzi4Ca0odGYPhpVLOuEwyiw78Qpb/hXL/FKvIUzb/hadDk+C/u1BpMiuAopap7LGSQ9NX35tH//2Ha2OWbzvGhr0PUIrl+8asXxui3vXpqZQRHCz9H8m0nIS+XHbCA0opov9ArgstJV8aGGE6w84UStGJgAFPXKTHHD7BI/gUvcngA+aQ+bTOaf6IxIWOl3JjzEF19B0weNzIHFrXhZc72HxxJdSMb1k4um/oJwp3JREBCL2oJ2G19530g==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VexCgqGZXIBtPx74pnNirFGRwBU2pun4dQ5jsviZ+3iOI5Ywk8WyOw5O40PIDfrZY2fvCbizKYsUsiRNroZUa1S+Qmhp51UZ93jlqDuPziUxkRxFncVPI6+yBhIC1/DCQhzISjkMbaVLJ7o+MGZkx6imqh03ENGSuG9b/QMyRyNnnUm29zVSmg2H3pcag2b1r/qUeubyOZZB6VM5qjcT41quVpCnA+JAeDKtjz5vhkaQyxVcnqD0ow+HxMTEGrvG/LT6HRzyD6f0yHC31C6D5IZmxM4zeKZYUgZZpWIsrFQRStKTf2R4WSFVACr3kPZn7gCm7Sq7oMlWzBzUTgjFlg==
- References: <37213fea-ae2e-0293-a042-9db2274cd061@suse.com>
There's just one bit of difference to the 32-bit element form, as
per the documentation.
gas/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* testsuite/gas/aarch64/f64mm.d,
testsuite/gas/aarch64/sve-movprfx-mm.d: Adjust expectations.
opcodes/
2020-01-XX Jan Beulich <jbeulich@suse.com>
* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
FMMLA encoding.
* opcodes/aarch64-dis-2.c: Re-generate.
--- a/gas/testsuite/gas/aarch64/f64mm.d
+++ b/gas/testsuite/gas/aarch64/f64mm.d
@@ -6,8 +6,8 @@
Disassembly of section \.text:
0+ <\.text>:
- *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
- *[0-9a-f]+: 64c0e400 fmmla z0\.d, z0\.d, z0\.d
+ *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d
*[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
*[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
*[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\]
--- a/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
+++ b/gas/testsuite/gas/aarch64/sve-movprfx-mm.d
@@ -21,4 +21,4 @@ Disassembly of section \.text:
*[0-9a-f]+: 0420bc11 movprfx z17, z0
*[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
*[0-9a-f]+: 0420bc11 movprfx z17, z0
- *[0-9a-f]+: 64dbe6b1 fmmla z17\.d, z21\.d, z27\.d
+ *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5073,7 +5073,7 @@ struct aarch64_opcode aarch64_opcode_tab
INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
- F64MATMUL_SVE_INSNC ("fmmla", 0x64c0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
+ F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0),
F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0),