[PATCH 6/7] RISC-V: Add support for XAndesVSIntH extension
Ethan Y. C. Liang
ycl669@andestech.com
Tue Nov 18 09:13:49 GMT 2025
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVSIntH extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVSIntH as an additional ISA extension for
Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvsinth string.
* testsuite/gas/riscv/x-andes-vsinth.d: New test.
* testsuite/gas/riscv/x-andes-vsinth.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVSINTH.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add INT4 vector load and INT4/INT8 vector
floating-point widening instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vsinth.d | 20 ++++++++++++++++++++
gas/testsuite/gas/riscv/x-andes-vsinth.s | 11 +++++++++++
include/opcode/riscv-opc.h | 17 +++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 7 +++++++
8 files changed, 67 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-andes-vsinth.d
create mode 100644 gas/testsuite/gas/riscv/x-andes-vsinth.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index dfd2b45b786..8a217203299 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1614,6 +1614,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xandesvsintload", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvpackfph", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvdot", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvsinth", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3010,6 +3011,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xandesvpackfph");
case INSN_CLASS_XANDESVDOT:
return riscv_subset_supports (rps, "xandesvdot");
+ case INSN_CLASS_XANDESVSINTH:
+ return riscv_subset_supports (rps, "xandesvsinth");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3331,6 +3334,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xandesvpackfph";
case INSN_CLASS_XANDESVDOT:
return "xandesvdot";
+ case INSN_CLASS_XANDESVSINTH:
+ return "xandesvsinth";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 698d789f424..398dd28d2a4 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -792,6 +792,11 @@ The XAndesVDot extension provides vector dot product instructions.
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVSIntH
+The XAndesVSIntH extension provides INT4 vector load and INT4/INT8 vector floating-point widening instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 791d5a61e58..d2481ab13b0 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -159,6 +159,7 @@ All available -march extensions for RISC-V:
xandesvsintload 5.0
xandesvpackfph 5.0
xandesvdot 5.0
+ xandesvsinth 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vsinth.d b/gas/testsuite/gas/riscv/x-andes-vsinth.d
new file mode 100644
index 00000000000..c507092e682
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vsinth.d
@@ -0,0 +1,20 @@
+#as: -march=rv32i_xandesvsinth
+#source: x-andes-vsinth.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0605425b[ ]+nds\.vle4\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0605425b[ ]+nds\.vle4\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0282425b[ ]+nds\.vfwcvt\.f\.n\.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+0082425b[ ]+nds\.vfwcvt\.f\.n\.v[ ]+v4,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+0282c25b[ ]+nds\.vfwcvt\.f\.nu\.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+0082c25b[ ]+nds\.vfwcvt\.f\.nu\.v[ ]+v4,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+0283425b[ ]+nds\.vfwcvt\.f\.b\.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+0083425b[ ]+nds\.vfwcvt\.f\.b\.v[ ]+v4,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+0283c25b[ ]+nds\.vfwcvt\.f\.bu\.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+0083c25b[ ]+nds\.vfwcvt\.f\.bu\.v[ ]+v4,v8,v0\.t
diff --git a/gas/testsuite/gas/riscv/x-andes-vsinth.s b/gas/testsuite/gas/riscv/x-andes-vsinth.s
new file mode 100644
index 00000000000..b97d00d6ad2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vsinth.s
@@ -0,0 +1,11 @@
+target:
+ nds.vle4.v v4, (a0)
+ nds.vle4.v v4, 0(a0)
+ nds.vfwcvt.f.n.v v4, v8
+ nds.vfwcvt.f.n.v v4, v8, v0.t
+ nds.vfwcvt.f.nu.v v4, v8
+ nds.vfwcvt.f.nu.v v4, v8, v0.t
+ nds.vfwcvt.f.b.v v4, v8
+ nds.vfwcvt.f.b.v v4, v8, v0.t
+ nds.vfwcvt.f.bu.v v4, v8
+ nds.vfwcvt.f.bu.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0c1bf8157d7..980dc6f1f41 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2547,6 +2547,17 @@
#define MASK_NDS_VD4DOTU_VV 0xfc00707f
#define MATCH_NDS_VD4DOTSU_VV 0x1400405b
#define MASK_NDS_VD4DOTSU_VV 0xfc00707f
+/* Vendor-specific (Andes) XAndesVSIntH instructions. */
+#define MATCH_NDS_VLE4_V 0x600405b
+#define MASK_NDS_VLE4_V 0xfff0707f
+#define MATCH_NDS_VFWCVT_F_N_V 0x2405b
+#define MASK_NDS_VFWCVT_F_N_V 0xfc0ff07f
+#define MATCH_NDS_VFWCVT_F_NU_V 0x2c05b
+#define MASK_NDS_VFWCVT_F_NU_V 0xfc0ff07f
+#define MATCH_NDS_VFWCVT_F_B_V 0x3405b
+#define MASK_NDS_VFWCVT_F_B_V 0xfc0ff07f
+#define MATCH_NDS_VFWCVT_F_BU_V 0x3c05b
+#define MASK_NDS_VFWCVT_F_BU_V 0xfc0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -4879,6 +4890,12 @@ DECLARE_INSN(nds_vfpmadb_vf, MATCH_NDS_VFPMADB_VF, MASK_NDS_VFPMADB_VF)
DECLARE_INSN(nds_vd4dots_vv, MATCH_NDS_VD4DOTS_VV, MASK_NDS_VD4DOTS_VV)
DECLARE_INSN(nds_vd4dotu_vv, MATCH_NDS_VD4DOTU_VV, MASK_NDS_VD4DOTU_VV)
DECLARE_INSN(nds_vd4dotsu_vv, MATCH_NDS_VD4DOTSU_VV, MASK_NDS_VD4DOTSU_VV)
+/* Vendor-specific (Andes) XAndesVSIntH instructions. */
+DECLARE_INSN(nds_vle4_v, MATCH_NDS_VLE4_V, MASK_NDS_VLE4_V)
+DECLARE_INSN(nds_vfwcvt_f_n_v, MATCH_NDS_VFWCVT_F_N_V, MASK_NDS_VFWCVT_F_N_V)
+DECLARE_INSN(nds_vfwcvt_f_nu_v, MATCH_NDS_VFWCVT_F_NU_V, MASK_NDS_VFWCVT_F_NU_V)
+DECLARE_INSN(nds_vfwcvt_f_b_v, MATCH_NDS_VFWCVT_F_B_V, MASK_NDS_VFWCVT_F_B_V)
+DECLARE_INSN(nds_vfwcvt_f_bu_v, MATCH_NDS_VFWCVT_F_BU_V, MASK_NDS_VFWCVT_F_BU_V)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 6fc52177f67..9d82e1c54f5 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -579,6 +579,7 @@ enum riscv_insn_class
INSN_CLASS_XANDESVSINTLOAD,
INSN_CLASS_XANDESVPACKFPH,
INSN_CLASS_XANDESVDOT,
+ INSN_CLASS_XANDESVSINTH,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7a308a8f403..1532306fc92 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2399,6 +2399,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.vd4dotu.vv", 0, INSN_CLASS_XANDESVDOT, "Vd,Vs,VtVm", MATCH_NDS_VD4DOTU_VV, MASK_NDS_VD4DOTU_VV, match_opcode, 0},
{"nds.vd4dotsu.vv", 0, INSN_CLASS_XANDESVDOT, "Vd,Vs,VtVm", MATCH_NDS_VD4DOTSU_VV, MASK_NDS_VD4DOTSU_VV, match_opcode, 0},
+/* Vendor-specific (Andes) XAndesVSIntH instructions. */
+{"nds.vle4.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,0(s)", MATCH_NDS_VLE4_V, MASK_NDS_VLE4_V, match_opcode, INSN_DREF},
+{"nds.vfwcvt.f.n.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_N_V, MASK_NDS_VFWCVT_F_N_V, match_opcode, 0},
+{"nds.vfwcvt.f.nu.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_NU_V, MASK_NDS_VFWCVT_F_NU_V, match_opcode, 0},
+{"nds.vfwcvt.f.b.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_B_V, MASK_NDS_VFWCVT_F_B_V, match_opcode, 0},
+{"nds.vfwcvt.f.bu.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_BU_V, MASK_NDS_VFWCVT_F_BU_V, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
--
2.49.0
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