[PATCH 7/7] RISC-V: Add support for XAndesVQMac extension
Ethan Y. C. Liang
ycl669@andestech.com
Tue Nov 18 09:13:50 GMT 2025
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVQMac extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVQMac as an additional ISA extension for
Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvqmac string.
* testsuite/gas/riscv/x-andes-vqmac.d: New test.
* testsuite/gas/riscv/x-andes-vqmac.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVQMAC.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add vector quad-widening integer
multiply-add instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vqmac.d | 24 ++++++++++++++++++++++++
gas/testsuite/gas/riscv/x-andes-vqmac.s | 15 +++++++++++++++
include/opcode/riscv-opc.h | 23 +++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 9 +++++++++
8 files changed, 83 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-andes-vqmac.d
create mode 100644 gas/testsuite/gas/riscv/x-andes-vqmac.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8a217203299..be65029215b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1615,6 +1615,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xandesvpackfph", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvdot", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvsinth", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvqmac", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3013,6 +3014,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xandesvdot");
case INSN_CLASS_XANDESVSINTH:
return riscv_subset_supports (rps, "xandesvsinth");
+ case INSN_CLASS_XANDESVQMAC:
+ return riscv_subset_supports (rps, "xandesvqmac");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3336,6 +3339,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xandesvdot";
case INSN_CLASS_XANDESVSINTH:
return "xandesvsinth";
+ case INSN_CLASS_XANDESVQMAC:
+ return "xandesvqmac";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 398dd28d2a4..f1abacec83d 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -797,6 +797,11 @@ The XAndesVSIntH extension provides INT4 vector load and INT4/INT8 vector floati
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVQMac
+The XAndesVQMac extension provides vector quad-widening integer multiply-add instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d2481ab13b0..cf62bc6225f 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -160,6 +160,7 @@ All available -march extensions for RISC-V:
xandesvpackfph 5.0
xandesvdot 5.0
xandesvsinth 5.0
+ xandesvqmac 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vqmac.d b/gas/testsuite/gas/riscv/x-andes-vqmac.d
new file mode 100644
index 00000000000..a06cd1fb2fb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vqmac.d
@@ -0,0 +1,24 @@
+#as: -march=rv32i_xandesvqmac
+#source: x-andes-vqmac.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+f2860257[ ]+nds\.vqmaccu\.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f0860257[ ]+nds\.vqmaccu\.vv[ ]+v4,v12,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+f285c257[ ]+nds\.vqmaccu\.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f085c257[ ]+nds\.vqmaccu\.vx[ ]+v4,a1,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+f6860257[ ]+nds\.vqmacc\.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+f4860257[ ]+nds\.vqmacc\.vv[ ]+v4,v12,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+f685c257[ ]+nds\.vqmacc\.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f485c257[ ]+nds\.vqmacc\.vx[ ]+v4,a1,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+fe860257[ ]+nds\.vqmaccsu\.vv[ ]+v4,v12,v8
+[ ]+[0-9a-f]+:[ ]+fc860257[ ]+nds\.vqmaccsu\.vv[ ]+v4,v12,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+fe85c257[ ]+nds\.vqmaccsu\.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+fc85c257[ ]+nds\.vqmaccsu\.vx[ ]+v4,a1,v8,v0\.t
+[ ]+[0-9a-f]+:[ ]+fa85c257[ ]+nds\.vqmaccus\.vx[ ]+v4,a1,v8
+[ ]+[0-9a-f]+:[ ]+f885c257[ ]+nds\.vqmaccus\.vx[ ]+v4,a1,v8,v0\.t
diff --git a/gas/testsuite/gas/riscv/x-andes-vqmac.s b/gas/testsuite/gas/riscv/x-andes-vqmac.s
new file mode 100644
index 00000000000..f78b72b40c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vqmac.s
@@ -0,0 +1,15 @@
+target:
+ nds.vqmaccu.vv v4, v12, v8
+ nds.vqmaccu.vv v4, v12, v8, v0.t
+ nds.vqmaccu.vx v4, a1, v8
+ nds.vqmaccu.vx v4, a1, v8, v0.t
+ nds.vqmacc.vv v4, v12, v8
+ nds.vqmacc.vv v4, v12, v8, v0.t
+ nds.vqmacc.vx v4, a1, v8
+ nds.vqmacc.vx v4, a1, v8, v0.t
+ nds.vqmaccsu.vv v4, v12, v8
+ nds.vqmaccsu.vv v4, v12, v8, v0.t
+ nds.vqmaccsu.vx v4, a1, v8
+ nds.vqmaccsu.vx v4, a1, v8, v0.t
+ nds.vqmaccus.vx v4, a1, v8
+ nds.vqmaccus.vx v4, a1, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 980dc6f1f41..9fb9fe65b12 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2558,6 +2558,21 @@
#define MASK_NDS_VFWCVT_F_B_V 0xfc0ff07f
#define MATCH_NDS_VFWCVT_F_BU_V 0x3c05b
#define MASK_NDS_VFWCVT_F_BU_V 0xfc0ff07f
+/* Vendor-specific (Andes) XAndesVQMac instructions. */
+#define MATCH_NDS_VQMACCU_VV 0xf0000057
+#define MASK_NDS_VQMACCU_VV 0xfc00707f
+#define MATCH_NDS_VQMACCU_VX 0xf0004057
+#define MASK_NDS_VQMACCU_VX 0xfc00707f
+#define MATCH_NDS_VQMACC_VV 0xf4000057
+#define MASK_NDS_VQMACC_VV 0xfc00707f
+#define MATCH_NDS_VQMACC_VX 0xf4004057
+#define MASK_NDS_VQMACC_VX 0xfc00707f
+#define MATCH_NDS_VQMACCSU_VV 0xfc000057
+#define MASK_NDS_VQMACCSU_VV 0xfc00707f
+#define MATCH_NDS_VQMACCSU_VX 0xfc004057
+#define MASK_NDS_VQMACCSU_VX 0xfc00707f
+#define MATCH_NDS_VQMACCUS_VX 0xf8004057
+#define MASK_NDS_VQMACCUS_VX 0xfc00707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -4896,6 +4911,14 @@ DECLARE_INSN(nds_vfwcvt_f_n_v, MATCH_NDS_VFWCVT_F_N_V, MASK_NDS_VFWCVT_F_N_V)
DECLARE_INSN(nds_vfwcvt_f_nu_v, MATCH_NDS_VFWCVT_F_NU_V, MASK_NDS_VFWCVT_F_NU_V)
DECLARE_INSN(nds_vfwcvt_f_b_v, MATCH_NDS_VFWCVT_F_B_V, MASK_NDS_VFWCVT_F_B_V)
DECLARE_INSN(nds_vfwcvt_f_bu_v, MATCH_NDS_VFWCVT_F_BU_V, MASK_NDS_VFWCVT_F_BU_V)
+/* Vendor-specific (Andes) XAndesVQMac instructions. */
+DECLARE_INSN(nds_vqmaccu_vv, MATCH_NDS_VQMACCU_VV, MASK_NDS_VQMACCU_VV)
+DECLARE_INSN(nds_vqmaccu_vx, MATCH_NDS_VQMACCU_VX, MASK_NDS_VQMACCU_VX)
+DECLARE_INSN(nds_vqmacc_vv, MATCH_NDS_VQMACC_VV, MASK_NDS_VQMACC_VV)
+DECLARE_INSN(nds_vqmacc_vx, MATCH_NDS_VQMACC_VX, MASK_NDS_VQMACC_VX)
+DECLARE_INSN(nds_vqmaccsu_vv, MATCH_NDS_VQMACCSU_VV, MASK_NDS_VQMACCSU_VV)
+DECLARE_INSN(nds_vqmaccsu_vx, MATCH_NDS_VQMACCSU_VX, MASK_NDS_VQMACCSU_VX)
+DECLARE_INSN(nds_vqmaccus_vx, MATCH_NDS_VQMACCUS_VX, MASK_NDS_VQMACCUS_VX)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 9d82e1c54f5..cf515e9fb4c 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -580,6 +580,7 @@ enum riscv_insn_class
INSN_CLASS_XANDESVPACKFPH,
INSN_CLASS_XANDESVDOT,
INSN_CLASS_XANDESVSINTH,
+ INSN_CLASS_XANDESVQMAC,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1532306fc92..a43d835f2ca 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2406,6 +2406,15 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.vfwcvt.f.b.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_B_V, MASK_NDS_VFWCVT_F_B_V, match_opcode, 0},
{"nds.vfwcvt.f.bu.v", 0, INSN_CLASS_XANDESVSINTH, "Vd,VtVm", MATCH_NDS_VFWCVT_F_BU_V, MASK_NDS_VFWCVT_F_BU_V, match_opcode, 0},
+/* Vendor-specific (Andes) XAndesVQMac instructions. */
+{"nds.vqmaccu.vv", 0, INSN_CLASS_XANDESVQMAC, "Vd,Vs,VtVm", MATCH_NDS_VQMACCU_VV, MASK_NDS_VQMACCU_VV, match_opcode, 0},
+{"nds.vqmaccu.vx", 0, INSN_CLASS_XANDESVQMAC, "Vd,s,VtVm", MATCH_NDS_VQMACCU_VX, MASK_NDS_VQMACCU_VX, match_opcode, 0},
+{"nds.vqmacc.vv", 0, INSN_CLASS_XANDESVQMAC, "Vd,Vs,VtVm", MATCH_NDS_VQMACC_VV, MASK_NDS_VQMACC_VV, match_opcode, 0},
+{"nds.vqmacc.vx", 0, INSN_CLASS_XANDESVQMAC, "Vd,s,VtVm", MATCH_NDS_VQMACC_VX, MASK_NDS_VQMACC_VX, match_opcode, 0},
+{"nds.vqmaccsu.vv", 0, INSN_CLASS_XANDESVQMAC, "Vd,Vs,VtVm", MATCH_NDS_VQMACCSU_VV, MASK_NDS_VQMACCSU_VV, match_opcode, 0},
+{"nds.vqmaccsu.vx", 0, INSN_CLASS_XANDESVQMAC, "Vd,s,VtVm", MATCH_NDS_VQMACCSU_VX, MASK_NDS_VQMACCSU_VX, match_opcode, 0},
+{"nds.vqmaccus.vx", 0, INSN_CLASS_XANDESVQMAC, "Vd,s,VtVm", MATCH_NDS_VQMACCUS_VX, MASK_NDS_VQMACCUS_VX, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
--
2.49.0
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