[PATCH 5/7] RISC-V: Add support for XAndesVDot extension
Ethan Y. C. Liang
ycl669@andestech.com
Tue Nov 18 09:13:48 GMT 2025
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVDot extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVDot as an additional ISA extension for
Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvdot string.
* testsuite/gas/riscv/x-andes-vdot.d: New test.
* testsuite/gas/riscv/x-andes-vdot.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVDOT.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add vector dot product instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vdot.d | 16 ++++++++++++++++
gas/testsuite/gas/riscv/x-andes-vdot.s | 7 +++++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 5 +++++
8 files changed, 51 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-andes-vdot.d
create mode 100644 gas/testsuite/gas/riscv/x-andes-vdot.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3fbc9bd8332..dfd2b45b786 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1613,6 +1613,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xandesvbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvsintload", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvpackfph", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvdot", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3007,6 +3008,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xandesvsintload");
case INSN_CLASS_XANDESVPACKFPH:
return riscv_subset_supports (rps, "xandesvpackfph");
+ case INSN_CLASS_XANDESVDOT:
+ return riscv_subset_supports (rps, "xandesvdot");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3326,6 +3329,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xandesvsintload";
case INSN_CLASS_XANDESVPACKFPH:
return "xandesvpackfph";
+ case INSN_CLASS_XANDESVDOT:
+ return "xandesvdot";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 216ddd8a895..698d789f424 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -787,6 +787,11 @@ The XAndesVPackFPH extension provides vector packed FP16 fused multiply-add inst
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVDot
+The XAndesVDot extension provides vector dot product instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 73d63828adf..791d5a61e58 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -158,6 +158,7 @@ All available -march extensions for RISC-V:
xandesvbfhcvt 5.0
xandesvsintload 5.0
xandesvpackfph 5.0
+ xandesvdot 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vdot.d b/gas/testsuite/gas/riscv/x-andes-vdot.d
new file mode 100644
index 00000000000..616f168f83b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vdot.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xandesvdot
+#source: x-andes-vdot.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+12c4425b[ ]+nds\.vd4dots\.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+10c4425b[ ]+nds\.vd4dots\.vv[ ]+v4,v8,v12,v0\.t
+[ ]+[0-9a-f]+:[ ]+1ec4425b[ ]+nds\.vd4dotu\.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+1cc4425b[ ]+nds\.vd4dotu\.vv[ ]+v4,v8,v12,v0\.t
+[ ]+[0-9a-f]+:[ ]+16c4425b[ ]+nds\.vd4dotsu\.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+14c4425b[ ]+nds\.vd4dotsu\.vv[ ]+v4,v8,v12,v0\.t
diff --git a/gas/testsuite/gas/riscv/x-andes-vdot.s b/gas/testsuite/gas/riscv/x-andes-vdot.s
new file mode 100644
index 00000000000..d836da7cbc0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vdot.s
@@ -0,0 +1,7 @@
+target:
+ nds.vd4dots.vv v4, v8, v12
+ nds.vd4dots.vv v4, v8, v12, v0.t
+ nds.vd4dotu.vv v4, v8, v12
+ nds.vd4dotu.vv v4, v8, v12, v0.t
+ nds.vd4dotsu.vv v4, v8, v12
+ nds.vd4dotsu.vv v4, v8, v12, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2180b20fd63..0c1bf8157d7 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2540,6 +2540,13 @@
#define MASK_NDS_VFPMADT_VF 0xfc00707f
#define MATCH_NDS_VFPMADB_VF 0xc00405b
#define MASK_NDS_VFPMADB_VF 0xfc00707f
+/* Vendor-specific (Andes) XAndesVDot instructions. */
+#define MATCH_NDS_VD4DOTS_VV 0x1000405b
+#define MASK_NDS_VD4DOTS_VV 0xfc00707f
+#define MATCH_NDS_VD4DOTU_VV 0x1c00405b
+#define MASK_NDS_VD4DOTU_VV 0xfc00707f
+#define MATCH_NDS_VD4DOTSU_VV 0x1400405b
+#define MASK_NDS_VD4DOTSU_VV 0xfc00707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -4868,6 +4875,10 @@ DECLARE_INSN(nds_vlnu8_v, MATCH_NDS_VLNU8_V, MASK_NDS_VLNU8_V)
/* Vendor-specific (Andes) XAndesVPackFPH instructions. */
DECLARE_INSN(nds_vfpmadt_vf, MATCH_NDS_VFPMADT_VF, MASK_NDS_VFPMADT_VF)
DECLARE_INSN(nds_vfpmadb_vf, MATCH_NDS_VFPMADB_VF, MASK_NDS_VFPMADB_VF)
+/* Vendor-specific (Andes) XAndesVDot instructions. */
+DECLARE_INSN(nds_vd4dots_vv, MATCH_NDS_VD4DOTS_VV, MASK_NDS_VD4DOTS_VV)
+DECLARE_INSN(nds_vd4dotu_vv, MATCH_NDS_VD4DOTU_VV, MASK_NDS_VD4DOTU_VV)
+DECLARE_INSN(nds_vd4dotsu_vv, MATCH_NDS_VD4DOTSU_VV, MASK_NDS_VD4DOTSU_VV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 8308bcd8c41..6fc52177f67 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -578,6 +578,7 @@ enum riscv_insn_class
INSN_CLASS_XANDESVBFHCVT,
INSN_CLASS_XANDESVSINTLOAD,
INSN_CLASS_XANDESVPACKFPH,
+ INSN_CLASS_XANDESVDOT,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 80dc2221288..7a308a8f403 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2394,6 +2394,11 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.vfpmadt.vf", 0, INSN_CLASS_XANDESVPACKFPH, "Vd,S,VtVm", MATCH_NDS_VFPMADT_VF, MASK_NDS_VFPMADT_VF, match_opcode, 0},
{"nds.vfpmadb.vf", 0, INSN_CLASS_XANDESVPACKFPH, "Vd,S,VtVm", MATCH_NDS_VFPMADB_VF, MASK_NDS_VFPMADB_VF, match_opcode, 0},
+/* Vendor-specific (Andes) XAndesVDot instructions. */
+{"nds.vd4dots.vv", 0, INSN_CLASS_XANDESVDOT, "Vd,Vs,VtVm", MATCH_NDS_VD4DOTS_VV, MASK_NDS_VD4DOTS_VV, match_opcode, 0},
+{"nds.vd4dotu.vv", 0, INSN_CLASS_XANDESVDOT, "Vd,Vs,VtVm", MATCH_NDS_VD4DOTU_VV, MASK_NDS_VD4DOTU_VV, match_opcode, 0},
+{"nds.vd4dotsu.vv", 0, INSN_CLASS_XANDESVDOT, "Vd,Vs,VtVm", MATCH_NDS_VD4DOTSU_VV, MASK_NDS_VD4DOTSU_VV, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
--
2.49.0
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