Add AMD znver5 RMPREAD instruction

[Jan Beulich]

On 28.01.2025 12:24, Kalvakuntla, Umesh wrote:
>> Well, for SNP - yes. What about e.g. CLZERO though? That also takes a memory
>> operand. Much like the various prefetch insns, just again with addressing limited to
>> just (%rax) / (%eax) / (%ax).
> 
> The intrinsics in both gcc and clang are taking single operand and are handling the mov of the argument. 
> Example assembly:
> movq    -40(%rbp), %rax
> clzero
> 
> So, we think it should be okay for CLZERO as it is currently.

Hmm, why does the same then not apply to RMPREAD and RMPUPDATE? CLZERO
is no different - it has no good way of spelling out a segment override
in particular, unless it was permitting

	clzero %gs:(%rax)

and then naturally also

	clzero (%rax)

Permitting the operand-less form for all three is quite okay for the
case where no overrides (segment or address size) are needed. Much like
is the case for string insns or XLAT (and is / should be for a few
others). Imo memory operands, no matter what variant of addressing they
use, would better all be spelled like memory operands.

Jan