[PATCH v1] RISC-V: Let fcvt.* recognize rounding mode != 0

[Jeff Law]

On 10/15/24 9:56 AM, Palmer Dabbelt wrote:
> On Tue, 15 Oct 2024 08:24:25 PDT (-0700), jeffreyalaw@gmail.com wrote:
>>
>>
>> On 10/15/24 9:17 AM, Nelson Chu wrote:
>>>
>>>
>>> On Tue, Oct 15, 2024 at 8:42 PM Jan Beulich <jbeulich@suse.com
>>> <mailto:jbeulich@suse.com>> wrote:
>>>
>>>     On 15.10.2024 11:30, Hau Hsu wrote:
>>>      > For those floating point convert instructions that convert 
>>> from lower
>>>      > precisions to higher precisions, although the rounding mode 
>>> has no
>>>      > effects, the spec doesn’t forbid them to be values other than 
>>> zero.
>>>
>>>     Yet what's the point of permitting the use of misleading operands?
>>>     In the
>>>     commit you refer to below I specifically said that the non- 
>>> standard 3-
>>>     operand forms are left merely to avoid breaking existing code. At 
>>> some
>>>     point I think use of them should actually be warned about, to allow
>>>     their
>>>     removal at a yet later point.
>>>
>>>
>>> Hey Jan,
>>>
>>> Personally, I agree and support that permitting the use of misleading
>>> operands looks weird, even though the random test generator people are
>>> always not happy about it.  Anway, I found this old discussion, https://
>>> github.com/riscv/riscv-isa-manual/issues/603 <https://github.com/riscv/
>>> riscv-isa-manual/issues/603>.  So...
>> Funny, I've got a complaint from our DV folks for the same issue.  I've
>> punted it so far, but I don't think they're particularly happy about it.
> 
> I thought we just told them to use `.insn` for this sort of stuff?  Did 
> that not work out?
I think that's what they're using.  But I don't think they're 
particularly happy about it.

jeff