[PATCH v1] RISC-V: Let fcvt.* recognize rounding mode != 0

[Andrew Waterman]

On Tue, Oct 15, 2024 at 8:17 AM Nelson Chu <nelson@rivosinc.com> wrote:
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> On Tue, Oct 15, 2024 at 8:42 PM Jan Beulich <jbeulich@suse.com> wrote:
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>> On 15.10.2024 11:30, Hau Hsu wrote:
>> > For those floating point convert instructions that convert from lower
>> > precisions to higher precisions, although the rounding mode has no
>> > effects, the spec doesn’t forbid them to be values other than zero.
>>
>> Yet what's the point of permitting the use of misleading operands? In the
>> commit you refer to below I specifically said that the non-standard 3-
>> operand forms are left merely to avoid breaking existing code. At some
>> point I think use of them should actually be warned about, to allow their
>> removal at a yet later point.
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> Hey Jan,
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> Personally, I agree and support that permitting the use of misleading operands looks weird, even though the random test generator people are always not happy about it.  Anway, I found this old discussion, https://github.com/riscv/riscv-isa-manual/issues/603.  So...
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> Hey Andrew,
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> Seems that this patch is trying to do the things that the above link mentioned - allow the unaffected rm field of fp widening conversion instructions.  Is this still valid now?  If that is so, then not only instructions in this patch need to be fixed.

Using a nonzero rm field is definitely legal at the ISA level.

I don't have a strong opinion on this one.  It's benign to allow
these, but they're only useful for DV, not application software.  If
that is (or isn't) deemed to be a good enough reason, fine by me, but
we should stay philosophically consistent going forward.

>
> Thanks
> Nelson