[PATCH v4 0/4] RISC-V: Combined floating point enhancements
Tsukasa OI
research_trasio@irq.a4lg.com
Sun Jul 24 18:58:54 GMT 2022
Before combining patchsets:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2)
<https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2)
Combined v1:
<https://sourceware.org/pipermail/binutils/2022-June/121138.html>
Combined v2:
<https://sourceware.org/pipermail/binutils/2022-June/121441.html>
Combined v3:
<https://sourceware.org/pipermail/binutils/2022-July/121720.html>
Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_float_combined>
This is a rebased and fixed version for Zfinx-related issues.
First, let me recap the changes.
1. Enhance Zfinx/Zdinx/Zqinx Testcases (PATCH 1/4)
I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
patch. I also...
- Made indentation / coding style consistent and clean
- Started to use valid register number on Zqinx
(as I explain below [PATCH 3-4/4])
- Started to use different register per operand
2. Relax Requirements to fmv.[sdq] instructions (PATCH 2/4)
On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
On RV32_Z[dq]inx and RV64_Zqinx, it requires register pair.
That means, single...
fmv.d x10, x12
is equivalent to 2 regular instructions on RV32_Zdinx (with 32-bit GPRs):
mv x10, x12
mv x11, x13
Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of Z[fdq]inx
extensions, it's safe to implement this pseudo-instructions.
This patch makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
3. Validate Register pairs on Zdinx/Zqinx (PATCH 3-4/4)
On RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must be even
(x0, x2, x4... are valid, x1, x3, x5... are invalid). On RV32_Zqinx, it would
be that all registers holding a FP128 value will be required to have a multiple
of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
On RV32_Zdinx, this is valid.
fadd.d x10, x12, x14
On the other hand, this is not valid (on RV32_Zdinx).
fadd.d x11, x13, x15
Current Binutils can generate invalid instructions with odd register numbers
(or register number x % 4 != 0). PATCH 3/4 makes those invalid.
Testcases (PATCH 4/4) are separate only because it is quite large.
[Changes: v3 -> v4]
- Rebased
- Fixed `fcvt.q.l{,u}' testcases (we don't need rounding anymore)
Clearly, I forgot to test the patchset.
This time, I confirmed that it passes the test.
[Changes: v2 -> v3]
- Rebased
- Postponed non-functional (coding style-related) changes
for another patchset
- Started to use `.insn r OP_FP, ...' on Z[dq]inx disassembler tests
- Fixed `fcvt.q.l{,u}' instruction match values
Tsukasa OI (4):
RISC-V: Reorganize and enhance Zfinx tests
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Validate Zdinx/Zqinx register pairs
RISC-V: Add testcases for Z[dq]inx register pairs
bfd/elfxx-riscv.c | 8 +
gas/config/tc-riscv.c | 21 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 ++++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 ++++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 27 +-
gas/testsuite/gas/riscv/zdinx.s | 46 +-
gas/testsuite/gas/riscv/zfinx.d | 24 +-
gas/testsuite/gas/riscv/zfinx.s | 42 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 +++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 +++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 +++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 +++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 +++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 +++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 84 +--
gas/testsuite/gas/riscv/zqinx.s | 87 +--
include/opcode/riscv.h | 10 +-
opcodes/riscv-opc.c | 541 ++++++++++++++----
31 files changed, 2097 insertions(+), 209 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: ea892bdc4b6da5782c6ea6273aff499fb5fd5e6f
--
2.34.1
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