[PATCH 0/9] RISC-V: Combined floating point enhancements
Tsukasa OI
research_trasio@irq.a4lg.com
Thu Jun 2 14:05:57 GMT 2022
PREVIOUS PATCHES:
<https://sourceware.org/pipermail/binutils/2022-May/120935.html> (Zfh/Zfhmin v2)
<https://sourceware.org/pipermail/binutils/2022-May/120940.html> (Zfinx v2)
[Combined Enhancements / Fixes]
0. Proper Zhinx/Zhinxmin support
1. Zfh/Zhinx refactoring / new Zfhmin/Zhinxmin support
<https://sourceware.org/pipermail/binutils/2022-May/120935.html>
<https://sourceware.org/pipermail/binutils/2022-May/120952.html>
2. Zfinx fixes / test enhancements
<https://sourceware.org/pipermail/binutils/2022-February/119570.html>
<https://sourceware.org/pipermail/binutils/2022-February/119576.html>
<https://sourceware.org/pipermail/binutils/2022-May/120940.html>
They are supposed to be separate but involves similar/same locations
that need to be modified. To ease testing and integration to upstream,
I decided to merge those fixes in a single patchset. Of course, I can
split it if requested.
Also in general, I squashed some of fixes/enhancements (spanned in
multiple patches) for simplicity.
As a result, it halved the number of patches (except Zhinx support, that
is new in this version).
Zfh/Zfhmin: 5 -> 3
Zfinx/Zdinx/Zqinx: 11 -> 5
[Details of Changes]
0.1. Add 'H' to canonical extension ordering (PATCH 01)
THIS IS DUPLICATE OF:
<https://sourceware.org/pipermail/binutils/2022-June/121115.html>
To implement Zhinx/Zhinxmin extensions, we have to determine where to
place Zh* extensions. To resolve this problem, I raised an issue on
RISC-V ISA Manual GitHub:
<https://github.com/riscv/riscv-isa-manual/issues/837>
...and we made a consensus. We will put 'H' after 'V'. Considering
compatibility with QEMU and LLVM, we can put 'H' after 'N' (making
'P' -> 'V' -> 'N' -> 'H' canonical ordering for compatibility).
Although this kind of canonical ordering is not ratified yet, it's at
least worth prototyping now.
This makes a difference. On a machine with GPR-FP support for 16, 32
and 64-bit floating point numbers, Jiawei's patch allows:
-march=rv64i_zhinx_zdinx
but my patch allows:
-march=rv64i_zdinx_zhinx
The latter will be canonical. But considering canonical ordering is
too much for regular developers, former should be made valid on future
patches.
1.1. Zfhmin/Zhinxmin subset extension support (PATCH 04)
This patch implements Zfhmin/Zhinxmin extension, conversion-only subset
of Zfh/Zhinx instruction set extensions, respectively.
1.2. [minor] Refactoring for better integration (PATCH 02)
In particular, better integration with F, D and Q. To do that, it
required moving certain macros and constants. But there are no
functional changes. The whole patchset would (and should) work without
this patch.
1.3. [minor] DECLARE_INSN declarations (PATCH 03)
Zfh instructions did not have their own DECLARE_INSN declarations.
PATCH 03 resolves this problem (although not having those is harmless
on current design).
2.1. Disassembler output with Zfinx + -M numeric option (PATCH 05)
Disassembling Zhinx/Zhinxmin/Zfinx/Zdinx/Zqinx instructions with -M
numeric option has an issue. It used ABI names instead of numeric one.
This commit fixes that.
2.2. Enhanced Zfinx/Zdinx/Zqinx testcases (PATCH 06)
I enhanced Zfinx/Zdinx/Zqinx testcases based on Jiawei's Zhinx support
patch. I also...
- Made indentation / coding style consistent and clean
- Started to use valid register number (on Zqinx)
- Started to use different register per operand
2.3. Relaxed requirements to fmv.[sdq] instructions (PATCH 07)
On Zfinx/Zdinx/Zqinx, fmv instructions seem redundant but actually not.
On RV32_Zdinx and RV64_Z[dq]inx, it requires register pair. That means,
single...
fmv.d x10, x12
is equivalent to 2 regular instructions on RV32_Zdinx (with 32b GPRs):
mv x10, x12
mv x11, x13
Since fsgnj.[sdq] (base instruction of fmv.[sdq]) are a part of
Z[fdq]inx extensions, it's safe to implement this pseudoinstructions.
PATCH 07 makes fmv.[sdq] available to Zfinx/Zdinx/Zqinx environments.
2.4. Validate register pairs on Zdinx/Zqinx (PATCH 08, 09)
For RV32_Zdinx and RV64_Zqinx, all registers holding a FP64 value must
be even (x0, x2, x4... are valid, x1, x3, x5... are invalid).
For RV32_Zqinx, it would be all registers holding a FP128 value must be
a multiple of 4 (x0, x4, x8... are valid, x1, x2, x3, x5... are not).
On the other hand, current Binutils can generate invalid instructions
with odd register numbers (or register number x % 4 != 0). PATCH 08
makes those invalid and PATCH 09 adds tests.
Due to complexity, this patch is relatively large.
Tsukasa OI (9):
RISC-V: Add 'H' to canonical extension ordering
RISC-V: Refactor Zfh/Zhinx-related constants
RISC-V: Add instruction declaration for Zfh/Zhinx
RISC-V: Add Zfhmin/Zhinxmin (with refactoring)
RISC-V: Fix disassembling Zfinx with -M numeric
RISC-V: Reorganize and enhance Zfinx tests
RISC-V: Relax `fmv.[sdq]' requirements
RISC-V: Validate Zdinx/Zqinx register pairs
RISC-V: Add testcases for Z[dq]inx register pairs
bfd/elfxx-riscv.c | 89 ++-
gas/config/tc-riscv.c | 39 +-
.../gas/riscv/zdinx-32-regpair-dis.d | 11 +
.../gas/riscv/zdinx-32-regpair-dis.s | 5 +
.../gas/riscv/zdinx-32-regpair-fail.d | 3 +
.../gas/riscv/zdinx-32-regpair-fail.l | 111 +++
.../gas/riscv/zdinx-32-regpair-fail.s | 116 +++
gas/testsuite/gas/riscv/zdinx-32-regpair.d | 65 ++
gas/testsuite/gas/riscv/zdinx-32-regpair.s | 62 ++
gas/testsuite/gas/riscv/zdinx.d | 27 +-
gas/testsuite/gas/riscv/zdinx.s | 46 +-
.../gas/riscv/zfhmin-d-insn-class-fail-1.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-1.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-2.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-3.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-4.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.d | 3 +
.../gas/riscv/zfhmin-d-insn-class-fail-5.l | 2 +
.../gas/riscv/zfhmin-d-insn-class-fail.s | 4 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.d | 10 +
gas/testsuite/gas/riscv/zfinx-dis-numeric.s | 2 +
gas/testsuite/gas/riscv/zfinx.d | 24 +-
gas/testsuite/gas/riscv/zfinx.s | 42 +-
.../gas/riscv/{fp-zhinx-insns.d => zhinx.d} | 37 +-
.../gas/riscv/{fp-zhinx-insns.s => zhinx.s} | 32 +-
.../gas/riscv/zqinx-32-regpair-dis.d | 12 +
.../gas/riscv/zqinx-32-regpair-dis.s | 7 +
.../gas/riscv/zqinx-32-regpair-fail.d | 3 +
.../gas/riscv/zqinx-32-regpair-fail.l | 212 ++++++
.../gas/riscv/zqinx-32-regpair-fail.s | 218 ++++++
gas/testsuite/gas/riscv/zqinx-32-regpair.d | 66 ++
gas/testsuite/gas/riscv/zqinx-32-regpair.s | 64 ++
.../gas/riscv/zqinx-64-regpair-dis.d | 11 +
.../gas/riscv/zqinx-64-regpair-dis.s | 5 +
.../gas/riscv/zqinx-64-regpair-fail.d | 3 +
.../gas/riscv/zqinx-64-regpair-fail.l | 133 ++++
.../gas/riscv/zqinx-64-regpair-fail.s | 138 ++++
gas/testsuite/gas/riscv/zqinx-64-regpair.d | 87 +++
gas/testsuite/gas/riscv/zqinx-64-regpair.s | 84 +++
gas/testsuite/gas/riscv/zqinx.d | 86 ++-
gas/testsuite/gas/riscv/zqinx.s | 89 ++-
include/opcode/riscv-opc.h | 180 +++--
include/opcode/riscv.h | 21 +-
opcodes/riscv-dis.c | 2 +-
opcodes/riscv-opc.c | 667 +++++++++++++-----
48 files changed, 2419 insertions(+), 419 deletions(-)
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zdinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
create mode 100644 gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.d
create mode 100644 gas/testsuite/gas/riscv/zfinx-dis-numeric.s
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.d => zhinx.d} (81%)
rename gas/testsuite/gas/riscv/{fp-zhinx-insns.s => zhinx.s} (85%)
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-32-regpair.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-dis.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.l
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair-fail.s
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.d
create mode 100644 gas/testsuite/gas/riscv/zqinx-64-regpair.s
base-commit: 625b6eae091709b95471eae92d42dc6bc71e6553
--
2.34.1
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