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Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- From: Leonid Yegoshin <Leonid dot Yegoshin at imgtec dot com>
- To: David Daney <ddaney at caviumnetworks dot com>
- Cc: Matthew Fortune <Matthew dot Fortune at imgtec dot com>, David Daney <david dot s dot daney at gmail dot com>, Rich Felker <dalias at libc dot org>, Andy Lutomirski <luto at amacapital dot net>, David Daney <ddaney dot cavm at gmail dot com>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>, "linux-kernel at vger dot kernel dot org" <linux-kernel at vger dot kernel dot org>, "linux-mips at linux-mips dot org" <linux-mips at linux-mips dot org>, David Daney <david dot daney at cavium dot com>
- Date: Tue, 7 Oct 2014 12:13:37 -0700
- Subject: Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
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- References: <1412627010-4311-1-git-send-email-ddaney dot cavm at gmail dot com> <20141006205459 dot GZ23797 at brightrain dot aerifal dot cx> <5433071B dot 4050606 at caviumnetworks dot com> <20141006213101 dot GA23797 at brightrain dot aerifal dot cx> <54330D79 dot 80102 at caviumnetworks dot com> <20141006215813 dot GB23797 at brightrain dot aerifal dot cx> <543327E7 dot 4020608 at amacapital dot net> <54332A64 dot 5020605 at caviumnetworks dot com> <20141007000514 dot GD23797 at brightrain dot aerifal dot cx> <543334CE dot 8060305 at caviumnetworks dot com> <20141007004915 dot GF23797 at brightrain dot aerifal dot cx> <54337127 dot 40806 at gmail dot com> <6D39441BF12EF246A7ABCE6654B0235320F1E173 at LEMAIL01 dot le dot imgtec dot org> <543431DA dot 4090809 at imgtec dot com> <5434343E dot 2090308 at caviumnetworks dot com>
(repeat it because of some e-mail failure, sorry)
On 10/07/2014 11:43 AM, David Daney wrote:
Five lines per instruction.
But you must be able to emulate them, so you need an emulator, not XOL.
I feel I didn't say clear - emulation of ADDIUPC (after second look it
is the only instruction requires a special handling) is A FIVE LINE OF
CODE. At least in MIPS R2 it would require 5 lines. In MIPS R2 emulator
I have some routine (50 lines) which checks BD-slot instruction for some
popular opcodes and emulates that and leave other opcodes to dsemul().
The same can be done for FPU emulator.
The problem is what to do with synchronous signals (SIGSEGV) Those
cannot be held off, and you really want the EPC value saved in the
register state to be correct.
Any synchronous exception is not a problem, we know that emulation in
VDSO (read today - stack) is running and should take care of it. We can
easily change EPC before we start doing signal and pretend that problem
happened in correct place.
The async signals seem to be some problem... yet... until I finish look
into common Linux kernel code, I think.
On 10/07/2014 11:44 AM, Andy Lutomirski wrote:
What happens if one of those out-of-line instructions causes a synchronous trap?
If we need to return that as signal then we change EPC to proper value
from emulframe->epc. If we do a nested emulation - continue.
> What if SIGSTOP arrives before ret?
I am looking into way to delay asynchronous signals until an emulated
instruction is finished. Signals are not time accurate and never been,
so it is not a big deal to delay it.
> What if another thread removes the magic ret sequence?
It can't do it in my approach, emulation is done in write protected area
and it is done in per-thread memory space.
- Leonid.