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Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- From: Leonid Yegoshin <Leonid dot Yegoshin at imgtec dot com>
- To: Matthew Fortune <Matthew dot Fortune at imgtec dot com>
- Cc: David Daney <david dot s dot daney at gmail dot com>, Rich Felker <dalias at libc dot org>, David Daney <ddaney at caviumnetworks dot com>, Andy Lutomirski <luto at amacapital dot net>, David Daney <ddaney dot cavm at gmail dot com>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>, "linux-kernel at vger dot kernel dot org" <linux-kernel at vger dot kernel dot org>, "linux-mips at linux-mips dot org" <linux-mips at linux-mips dot org>, David Daney <david dot daney at cavium dot com>
- Date: Tue, 7 Oct 2014 11:32:58 -0700
- Subject: Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- Authentication-results: sourceware.org; auth=none
- References: <1412627010-4311-1-git-send-email-ddaney dot cavm at gmail dot com> <20141006205459 dot GZ23797 at brightrain dot aerifal dot cx> <5433071B dot 4050606 at caviumnetworks dot com> <20141006213101 dot GA23797 at brightrain dot aerifal dot cx> <54330D79 dot 80102 at caviumnetworks dot com> <20141006215813 dot GB23797 at brightrain dot aerifal dot cx> <543327E7 dot 4020608 at amacapital dot net> <54332A64 dot 5020605 at caviumnetworks dot com> <20141007000514 dot GD23797 at brightrain dot aerifal dot cx> <543334CE dot 8060305 at caviumnetworks dot com> <20141007004915 dot GF23797 at brightrain dot aerifal dot cx> <54337127 dot 40806 at gmail dot com> <6D39441BF12EF246A7ABCE6654B0235320F1E173 at LEMAIL01 dot le dot imgtec dot org>
Well, I am not a subscriber to mail-list, so I read it the first time
and some notes:
1) David's approach would likely work for FPU emulation but unlikely
works for MIPS Rel 2/Rel 1/ MIPS I emulation in MIPS R6 architecture.
The reason is that the first MIPS R2 instruction (removed from MIPS R6)
can be hit long before GLIBC/bionic/etc can determine how to use
properly a new system call. And that instruction needs to be emulated. I
actually hit this problem with ssh-keygen first and referred to FPU
emulation because I got it later, during my attempt to salvage a situation.
2) The issue of uMIPS ADDIUPC and similar instructions are overblown in
my opinion. Never of them are memory-related and their emulation in
BD-slot can be easily done in kernel and that actually accelerates an
emulation. Look at piece of code which I wrote to accelerate an
emulation of some instructions in BD-slot of JR instruction:
switch (MIPSInst_OPCODE(ir)) {
case addiu_op:
if (MIPSInst_RT(ir))
regs->regs[MIPSInst_RT(ir)] =
(s32)regs->regs[MIPSInst_RS(ir)] +
(s32)MIPSInst_SIMM(ir);
return(0);
#ifdef CONFIG_64BIT
case daddiu_op:
if (MIPSInst_RT(ir))
regs->regs[MIPSInst_RT(ir)] =
(s64)regs->regs[MIPSInst_RS(ir)] +
(s64)MIPSInst_SIMM(ir);
return(0);
#endif
Five lines per instruction.
3) The signal happened during execution of emulated instruction -
signals are under control of kernel and we can easily delay a signal
during execution of emulated instruction until return from do_dsemulret.
It is not a big deal - nor code, nor performance. Thank you for good point.
4) The voice for doing any instruction emulation in kernel - it is not
a MIPS business model to force customer to put details of all
Coprocessor 2 instructions public. We provide an interface and the rest
is a customer business. Besides that it is really painful to make a
differentiation between Cavium Octeon and some another CPU instructions
with the same opcode. On other side, leaving emulation of their
instructions to them is not a wise after having some good way doing that
multiple years.
- Leonid.