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Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
- From: Rich Felker <dalias at libc dot org>
- To: Andy Lutomirski <luto at amacapital dot net>
- Cc: Leonid Yegoshin <Leonid dot Yegoshin at imgtec dot com>, Matthew Fortune <Matthew dot Fortune at imgtec dot com>, David Daney <david dot s dot daney at gmail dot com>, David Daney <ddaney at caviumnetworks dot com>, David Daney <ddaney dot cavm at gmail dot com>, "libc-alpha at sourceware dot org" <libc-alpha at sourceware dot org>, "linux-kernel at vger dot kernel dot org" <linux-kernel at vger dot kernel dot org>, "linux-mips at linux-mips dot org" <linux-mips at linux-mips dot org>, David Daney <david dot daney at cavium dot com>
- Date: Tue, 7 Oct 2014 15:09:43 -0400
- Subject: Re: [PATCH resend] MIPS: Allow FPU emulator to use non-stack area.
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On Tue, Oct 07, 2014 at 11:44:35AM -0700, Andy Lutomirski wrote:
> > 4) The voice for doing any instruction emulation in kernel - it is not a
> > MIPS business model to force customer to put details of all Coprocessor 2
> > instructions public. We provide an interface and the rest is a customer
> > business. Besides that it is really painful to make a differentiation
> > between Cavium Octeon and some another CPU instructions with the same
> > opcode. On other side, leaving emulation of their instructions to them is
> > not a wise after having some good way doing that multiple years.
>
> IMO this is all backwards. If MIPS customers put proprietary
> instructions into their ISA, they leave out the FPU, and they put a
> proprietary insn in a branch delay slot, then I think that they
> deserve a fatal signal.
I agree completely here. We should not break things (or, as it seems,
leave them broken) for common usage cases that affect everyone just to
coddle proprietary vendor-specific instructions. The latter just
should not be used in delay slots unless the chip vendor also promises
to provide fpu branch in hardware.
Rich