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[PATCH RESEND] x86: allow VEX et al encodings in 16-bit (protected) mode

These encodings aren't valid in real and VM86 modes, but they are very
well usable in 16-bit protected mode.

A few adjustments in the disassembler tables are needed where Ev or Gv
were wrongly used. Additionally an adjustment is needed to avoid
printing "addr32" when that's already recognizable by the use of %eiz.

Furthermore the Iq operand template was wrong for XOP:0Ah encoding
insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
Id instead.

Clone a few existing test cases to exercise assembler and disassembler.

2019-06-24  Jan Beulich  <>

	config/tc-i386.c (md_assemble): Check for protected mode
	incapable processor before encoding VEX and alike insns.
	* testsuite/gas/i386/inval-16.s: For 80186 architecture.
	* testsuite/gas/i386/inval-16.l: Adjust expectations.
	* testsuite/gas/i386/avx-16bit.d,
	testsuite/gas/i386/lwp-16bit.s: New
	testsuite/gas/i386/i386.exp: Run new tests.

2019-06-24  Jan Beulich  <>

	* i386-dis.c (Iq): Delete.
	(Id): New.
	(reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
	TBM insns.
	(vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
	vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
	(OP_E_memory): Also honor needindex when deciding whether an
	address size prefix needs printing.
	(OP_I): Remove handling of q_mode. Add handling of d_mode.

Re-sending with the actual patch a compressed attachment, as it
appears to be larger than what the list would accept.


Attachment: binutils-master-x86-VEX-16bit.patch.bz2
Description: Binary data

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