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Re: [PATCH RESEND] x86: allow VEX et al encodings in 16-bit (protected) mode


On Mon, Jun 24, 2019 at 7:05 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> These encodings aren't valid in real and VM86 modes, but they are very
> well usable in 16-bit protected mode.
>
> A few adjustments in the disassembler tables are needed where Ev or Gv
> were wrongly used. Additionally an adjustment is needed to avoid
> printing "addr32" when that's already recognizable by the use of %eiz.
>
> Furthermore the Iq operand template was wrong for XOP:0Ah encoding
> insns: They're having a uniform 32-bit immediate. Drop Iq and introduce
> Id instead.
>
> Clone a few existing test cases to exercise assembler and disassembler.
>
> gas/
> 2019-06-24  Jan Beulich  <jbeulich@suse.com>
>
>         config/tc-i386.c (md_assemble): Check for protected mode
>         incapable processor before encoding VEX and alike insns.
>         * testsuite/gas/i386/inval-16.s: For 80186 architecture.
>         * testsuite/gas/i386/inval-16.l: Adjust expectations.
>         * testsuite/gas/i386/avx-16bit.d,
>         testsuite/gas/i386/avx-16bit.s,
>         testsuite/gas/i386/avx512f-16bit.d,
>         testsuite/gas/i386/avx512f-16bit.s,
>         testsuite/gas/i386/bmi-16bit.d,
>         testsuite/gas/i386/bmi-16bit.s,
>         testsuite/gas/i386/bmi2-16bit.d,
>         testsuite/gas/i386/bmi2-16bit.s,
>         testsuite/gas/i386/lwp-16bit.d,
>         testsuite/gas/i386/lwp-16bit.s: New
>         testsuite/gas/i386/i386.exp: Run new tests.
>
> opcodes/
> 2019-06-24  Jan Beulich  <jbeulich@suse.com>
>
>         * i386-dis.c (Iq): Delete.
>         (Id): New.
>         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
>         TBM insns.
>         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
>         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
>         (OP_E_memory): Also honor needindex when deciding whether an
>         address size prefix needs printing.
>         (OP_I): Remove handling of q_mode. Add handling of d_mode.
>
> Re-sending with the actual patch a compressed attachment, as it
> appears to be larger than what the list would accept.
>
> Jan
>
>
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -4387,9 +4387,9 @@ md_assemble (char *line)
>
>    if (is_any_vex_encoding (&i.tm))
>      {
> -      if (flag_code == CODE_16BIT)
> +      if (!cpu_arch_flags.bitfield.cpui286)
>         {
> -         as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
> +         as_bad (_("instruction `%s' isn't supported outside of protected mode."),
>                   i.tm.name);
>           return;
>         }

flag_code == CODE_16BIT is used to indicate 16-bit mode, in most cases, for real
mode.   If there are real use cases for VEX/EVEX insns in 16-bit protected mode,
should we add a directive or pseudo prefix to indicate protected mode encoding?

-- 
H.J.


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