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V3: [PATCH] x32: Generate 0x67 prefix for VSIB address without base

From: "H.J. Lu" <hjl dot tools at gmail dot com>
To: Jan Beulich <JBeulich at suse dot com>
Cc: Binutils <binutils at sourceware dot org>
Date: Tue, 26 Feb 2019 12:33:18 -0800
Subject: V3: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
References: <20190225140212.7737-1-hjl.tools@gmail.com> <5C74064C0200007800219F31@prv1-mh.provo.novell.com> <CAMe9rOr08jU4Pi6OjuqqbLYC+c513Ky-DR_F+1cCn6UcyJEg=A@mail.gmail.com> <5C741560020000780021A002@prv1-mh.provo.novell.com> <CAMe9rOofzOj=LAZ9h6q0C5=0TsWw2SM3oifiq1VukkczZD7tRg@mail.gmail.com> <CAMe9rOpss_CcbYr0_dm2Jccf03TbifSY=W1JKKYs0k1+tftT-Q@mail.gmail.com> <20190226043508.GA6382@gmail.com> <5C7525F6020000780021A4C1@prv1-mh.provo.novell.com> <CAMe9rOqd0RwY3XLpH=J7aFLijewZP3qFH60PyXtYe+2=o8XzYA@mail.gmail.com> <5C75510B020000780021A58A@prv1-mh.provo.novell.com> <CAMe9rOr7H1=ANTZToQA27PeiJ=mQKf=dhMFd5M4Dk7mqbczn_Q@mail.gmail.com> <5C756657020000780021A667@prv1-mh.provo.novell.com>

On Tue, Feb 26, 2019 at 8:16 AM Jan Beulich <JBeulich@suse.com> wrote:
>
> >>> On 26.02.19 at 17:07, <hjl.tools@gmail.com> wrote:
> > On Tue, Feb 26, 2019 at 6:45 AM Jan Beulich <JBeulich@suse.com> wrote:
> >>
> >> >>> On 26.02.19 at 14:23, <hjl.tools@gmail.com> wrote:
> >> > On Tue, Feb 26, 2019 at 3:41 AM Jan Beulich <JBeulich@suse.com> wrote:
> >> >>
> >> >> >>> On 26.02.19 at 05:35, <hjl.tools@gmail.com> wrote:
> >> >> > In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address without base
> >> >> > register so that vector index register will be zero-extended to 64 bits.
> >> >> >
> >> >> > We can't have ADDR_PREFIX_OPCODE prefix with 32-bit address if there is
> >> >> > segment override since address will be segment base + zero-extended to 64
> >> >> > bits of (base + index * scale + disp).  But GCC:
> >> >> >
> >> >> > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89502
> >> >>
> >> >> Neither above nor in the bug you explain what's wrong with the
> >> >> segment override plus address size override in x32 mode. Since you
> >> >
> >> > X32 relies on 0x67 prefix to zero-extend address to 64 bits:
> >> >
> >> > zero-extended (base + index * scale + disp)
> >> >
> >> > With segment override, we got
> >> >
> >> > segment base + zero-extended (base + index * scale + disp)
> >> >
> >> > instead of
> >> >
> >> > zero-extended (segment base + base + index * scale + disp)
> >> >
> >> > When base + index * scale + disp is negative, we get the wrong
> >> > address.
> >> >
> >> > VSIB address in vgatherdps is
> >> >
> >> > base + sign-extend(index) * scale + disp
> >> >
> >> > With segment override, we got
> >> >
> >> > segment base + zero-extended (base + sign-extend(index) * scale + disp)
> >>
> >> Right. But whether that's what the programmer wanted we don't
> >> know. Also please consider the qword index forms as well, plus
> >> the dword index forms with scaling factor 2, 4, or 8 (allowing for
> >> effective indexes up to 35 bits wide).
> >>
> >> All of this would be acceptable if address space was limited to 4Gb
> >> for x32, but that's not the case according to my reading of the
> >> chapter in the psABI.
> >
> > 10.4 Kernel Support
> > Kernel should limit stack and addresses returned from system calls
> > bewteen 0x00000000
> > to 0xf f f f f f f f .
>
> Hmm, if that's indeed the case, despite it - according to my
> interpretation - contradicting 10.2's wording, and despite it
> being an unnecessary restriction imo, then ...
>
> >> > 175.vpr in SPEC CPU 2000:
> >> >[...]
> >> > Program received signal SIGSEGV, Segmentation fault.
> >> > 0x004158fd in try_place.isra ()
> >> > (gdb) disass 0x004158fd,+32
> >> > Dump of assembler code from 0x4158fd to 0x41591d:
> >> > => 0x004158fd <try_place.isra.5+7517>: vgatherdps %ymm2,0xc(,%ymm15,1),%ymm12
> >>
> >> Okay, this is the special case of the index register actually holding
> >> addresses. What about the case where the displacement is the base
> >> address, and the index register holds indeed indexes?
> >
> > I will fix it.
>
> ... there's nothing to fix here, I think.
>

Here is the updated patch.  I added VecSIBQword to mark VSIB instructions
with Qword indices and add 0x67 prefix only for VSIB address of Dword
indices without base register nor symbol so that Dword indices will be
zero-extended to 64 bits unless -moperand-check=none is passed to
assembler.

-- 
H.J.

From 0acb4c8e53992f598cc46929515c92f90c544bd4 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Sun, 24 Feb 2019 18:38:33 -0800
Subject: [PATCH] x32: Generate 0x67 prefix for VSIB address if needed

Dword indices in VSIB address are sign-extended to 64 bits.  In x32, add
ADDR_PREFIX_OPCODE prefix for VSIB address of Dword indices without base
register nor symbol so that Dword indices will be zero-extended to 64 bits
unless -moperand-check=none is passed to assembler.

We can't have ADDR_PREFIX_OPCODE prefix with 32-bit address if there is
segment override since address will be

segment base + zero-extend(base + index * scale + disp)

instead of

zero-extend (segment base + base + index * scale + disp)

The address will be wrong if (base + index * scale + disp) is negative.
But GCC:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89502

may generate

	movl	$24, %edx
	movl	%fs:(%edx), %ecx

instead of

	movl	%fs:24, %ecx

So a warning:

Warning: segment `%fs' override with 32-bit address

is issued by default.  -moperand-check=error will turn a warning into
an error.

Error: segment `%fs' override with 32-bit address

gas/

	PR gas/24263
	* config/tc-i386.c (output_insn): In x32, add 0x67 address size
	prefix for VSIB address of Dword indices without base register nor
	symbol.  Issue a warning or an error for segment override with
	ADDR_PREFIX_OPCODE prefix.
	* testsuite/gas/i386/ilp32/ilp32.exp: Run x86-64-seg-inval.
	* testsuite/gas/i386/ilp32/x86-64-seg-inval.l: New file.
	* testsuite/gas/i386/ilp32/x86-64-seg-inval.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg-none.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg-none.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg-warn.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg-warn.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg.s: Likewise.

opcodes/

	PR gas/24263
	* i386-gen.c (opcode_modifiers): Add VecSIBQword.
	* i386-opc.h (VecSIBQword): New.
	(i386_opcode_modifier): Add vecsibqword.
	* i386-opc.tbl: Add VecSIBQword to VSIB instructions with Qword
	indices.
	* i386-tbl.h: Regenerated.
---
 gas/config/tc-i386.c                          |    54 +
 gas/testsuite/gas/i386/ilp32/ilp32.exp        |     1 +
 .../gas/i386/ilp32/x86-64-seg-inval.l         |     5 +
 .../gas/i386/ilp32/x86-64-seg-inval.s         |     7 +
 .../gas/i386/ilp32/x86-64-seg-none.d          |    16 +
 .../gas/i386/ilp32/x86-64-seg-none.s          |     3 +
 .../gas/i386/ilp32/x86-64-seg-warn.d          |    16 +
 .../gas/i386/ilp32/x86-64-seg-warn.e          |     5 +
 gas/testsuite/gas/i386/ilp32/x86-64-seg.d     |   212 +
 gas/testsuite/gas/i386/ilp32/x86-64-seg.s     |    14 +
 opcodes/i386-gen.c                            |     1 +
 opcodes/i386-opc.h                            |     6 +
 opcodes/i386-opc.tbl                          |    80 +-
 opcodes/i386-tbl.h                            | 11682 ++++++++++------
 14 files changed, 8168 insertions(+), 3934 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-none.d
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-none.s
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.d
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d31ee6abdd..b1e6460a1c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8141,6 +8141,60 @@ output_insn (void)
 	  i.prefix[LOCK_PREFIX] = 0;
 	}
 
+#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
+      if (operand_check != check_none
+	  && flag_code == CODE_64BIT
+	  && x86_elf_abi == X86_64_X32_ABI)
+	{
+	  if (i.tm.opcode_modifier.vecsib)
+	    {
+	      if (!i.tm.opcode_modifier.vecsibqword
+		  && !i.base_reg
+		  && !i.prefix[SEG_PREFIX])
+		{
+		  unsigned int op;
+		  for (op = 0; op < i.operands; op++)
+		    if (operand_type_check (i.types[op], disp))
+		      break;
+		  if (op == i.operands)
+		    abort ();
+		  switch (i.op[op].disps->X_op)
+		    {
+		    default:
+		      abort ();
+		    case O_constant:
+		      /* Dword indices in VSIB address are sign-extended
+			 to 64 bits.  In x32, add ADDR_PREFIX_OPCODE
+			 prefix for VSIB address of Dword indices without
+			 base register nor symbol so that Dword indices
+			 will be zero-extended to 64 bits.  */
+		      add_prefix (ADDR_PREFIX_OPCODE);
+		      break;
+		    case O_symbol:
+		      break;
+		    }
+		}
+	    }
+	  else if (i.prefix[ADDR_PREFIX] && i.prefix[SEG_PREFIX])
+	    {
+	      /* In x32, we can't have ADDR_PREFIX_OPCODE prefix with
+		 segment override since final address will be segment
+		 base + zero-extended (base + index * scale + disp).  */
+	      const seg_entry *seg;
+	      if (i.seg[0])
+		seg = i.seg[0];
+	      else
+		seg = i.seg[1];
+	      if (operand_check == check_error)
+		as_bad (_("segment `%s%s' override with 32-bit address"),
+			register_prefix, seg->seg_name);
+	      else
+		as_warn (_("segment `%s%s' override with 32-bit address"),
+			 register_prefix, seg->seg_name);
+	    }
+	}
+#endif
+
       /* Since the VEX/EVEX prefix contains the implicit prefix, we
 	 don't need the explicit prefix.  */
       if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
diff --git a/gas/testsuite/gas/i386/ilp32/ilp32.exp b/gas/testsuite/gas/i386/ilp32/ilp32.exp
index d3a7190ac5..fe1e9ea5df 100644
--- a/gas/testsuite/gas/i386/ilp32/ilp32.exp
+++ b/gas/testsuite/gas/i386/ilp32/ilp32.exp
@@ -38,6 +38,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_x32_check] &
     }
 
     run_list_test "reloc64" "--defsym _bad_=1"
+    run_list_test "x86-64-seg-inval" "-moperand-check=error"
 
     set ASFLAGS "$old_ASFLAGS"
 }
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
new file mode 100644
index 0000000000..a139dea2ae
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:4: Error: segment `%fs' override with 32-bit address
+.*:5: Error: segment `%fs' override with 32-bit address
+.*:6: Error: segment `%gs' override with 32-bit address
+.*:7: Error: segment `%gs' override with 32-bit address
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
new file mode 100644
index 0000000000..455e18c628
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
@@ -0,0 +1,7 @@
+	.text
+	.allow_index_reg
+_start:
+	movl	%fs:(%eax), %eax
+	movl	%fs:(,%eax,1), %eax
+	movl	%gs:(,%eiz,1), %eax
+	movl	%gs:(%eip), %eax
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.d
new file mode 100644
index 0000000000..1792ef70a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.d
@@ -0,0 +1,16 @@
+#source: x86-64-seg-none.s
+#as: -moperand-check=none -I$srcdir/$subdir
+#objdump: -dw
+#name: x86-64 (ILP32) segment check (none)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	64 67 8b 00          	mov    %fs:\(%eax\),%eax
+ +[a-f0-9]+:	64 67 8b 04 05 00 00 00 00 	mov    %fs:0x0\(,%eax,1\),%eax
+ +[a-f0-9]+:	65 67 8b 04 25 00 00 00 00 	mov    %gs:0x0\(,%eiz,1\),%eax
+ +[a-f0-9]+:	65 67 8b 05 00 00 00 00 	mov    %gs:0x0\(%eip\),%eax        # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+ +[a-f0-9]+:	c4 22 1d 92 1c 3d 0c 00 00 00 	vgatherdps %ymm12,0xc\(,%ymm15,1\),%ymm11
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.s
new file mode 100644
index 0000000000..37c84e81f5
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-none.s
@@ -0,0 +1,3 @@
+.include "x86-64-seg-inval.s"
+
+	vgatherdps	%ymm12,0xc(,%ymm15,1),%ymm11
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
new file mode 100644
index 0000000000..a3295e8e5c
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
@@ -0,0 +1,16 @@
+#source: x86-64-seg-inval.s
+#as: -moperand-check=warning
+#warning_output: x86-64-seg-warn.e
+#objdump: -dw
+#name: x86-64 (ILP32) segment check (warning)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	64 67 8b 00          	mov    %fs:\(%eax\),%eax
+ +[a-f0-9]+:	64 67 8b 04 05 00 00 00 00 	mov    %fs:0x0\(,%eax,1\),%eax
+ +[a-f0-9]+:	65 67 8b 04 25 00 00 00 00 	mov    %gs:0x0\(,%eiz,1\),%eax
+ +[a-f0-9]+:	65 67 8b 05 00 00 00 00 	mov    %gs:0x0\(%eip\),%eax        # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
new file mode 100644
index 0000000000..fb0191a529
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:4: Warning: segment `%fs' override with 32-bit address
+.*:5: Warning: segment `%fs' override with 32-bit address
+.*:6: Warning: segment `%gs' override with 32-bit address
+.*:7: Warning: segment `%gs' override with 32-bit address
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
new file mode 100644
index 0000000000..0bda5e3ffc
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
@@ -0,0 +1,212 @@
+#as: -I$srcdir/$subdir
+#objdump: -dw
+#name: x86-64 (ILP32) segment
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	c4 e2 e9 92 4c 7d 00 	vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 93 4c 7d 00 	vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 92 4c 7d 00 	vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 93 4c 7d 00 	vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 92 5c 75 00 	vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 93 5c 75 00 	vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 92 5c 75 00 	vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 93 5c 75 00 	vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 69 92 4c 7d 00 	vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 92 4c 7d 00 	vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 92 5c 75 00 	vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 92 5c 75 00 	vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 69 90 4c 7d 00 	vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 90 4c 7d 00 	vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 90 5c 75 00 	vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 90 5c 75 00 	vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 e9 90 4c 7d 00 	vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 91 4c 7d 00 	vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 90 4c 7d 00 	vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 91 4c 7d 00 	vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 90 5c 75 00 	vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 91 5c 75 00 	vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 90 5c 75 00 	vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 91 5c 75 00 	vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 e9 92 4c 7d 00 	vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 93 4c 7d 00 	vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 92 4c 7d 00 	vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 93 4c 7d 00 	vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 92 5c 75 00 	vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 93 5c 75 00 	vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 92 5c 75 00 	vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 93 5c 75 00 	vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 69 92 4c 7d 00 	vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 92 4c 7d 00 	vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 92 5c 75 00 	vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 92 5c 75 00 	vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 69 90 4c 7d 00 	vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 90 4c 7d 00 	vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 90 5c 75 00 	vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 90 5c 75 00 	vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 e9 90 4c 7d 00 	vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 91 4c 7d 00 	vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 90 4c 7d 00 	vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 91 4c 7d 00 	vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 90 5c 75 00 	vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 91 5c 75 00 	vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 90 5c 75 00 	vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 91 5c 75 00 	vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	64 8b 04 25 00 00 00 00 	mov    %fs:0x0,%eax
+ +[a-f0-9]+:	65 8b 05 00 00 00 00 	mov    %gs:0x0\(%rip\),%eax        # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+ +[a-f0-9]+:	65 8b 00             	mov    %gs:\(%rax\),%eax
+ +[a-f0-9]+:	c4 22 1d 93 1c 3d 00 00 00 00 	vgatherqps %xmm12,0x0\(,%ymm15,1\),%xmm11
+ +[a-f0-9]+:	c4 22 1d 93 1c 3d 00 00 00 00 	vgatherqps %xmm12,0x0\(,%ymm15,1\),%xmm11
+ +[a-f0-9]+:	c4 22 1d 93 1c 3d 0c 00 00 00 	vgatherqps %xmm12,0xc\(,%ymm15,1\),%xmm11
+ +[a-f0-9]+:	c4 22 1d 92 1c 3d 00 00 00 00 	vgatherdps %ymm12,0x0\(,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	c4 22 1d 92 1c 3d 00 00 00 00 	vgatherdps %ymm12,0x0\(,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	67 c4 22 1d 92 5c 38 0c 	vgatherdps %ymm12,0xc\(%eax,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	64 c4 22 1d 92 5c 38 0c 	vgatherdps %ymm12,%fs:0xc\(%rax,%ymm15,1\),%ymm11
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
new file mode 100644
index 0000000000..2a37d127a4
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
@@ -0,0 +1,14 @@
+.include "../x86-64-avx-gather.s"
+
+	.text
+	.att_syntax
+	movl	%fs:0, %eax
+	movl	%gs:(%rip), %eax
+	movl	%gs:(%rax), %eax
+	vgatherqps	%xmm12,foo(,%ymm15,1),%xmm11
+	vgatherqps	%xmm12,foo+1(,%ymm15,1),%xmm11
+	vgatherqps	%xmm12,0xc(,%ymm15,1),%xmm11
+	vgatherdps	%ymm12,foo(,%ymm15,1),%ymm11
+	vgatherdps	%ymm12,foo+1(,%ymm15,1),%ymm11
+	vgatherdps	%ymm12,0xc(%eax,%ymm15,1),%ymm11
+	vgatherdps	%ymm12,%fs:0xc(%rax,%ymm15,1),%ymm11
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index af74b59479..ea7019e871 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -645,6 +645,7 @@ static bitfield opcode_modifiers[] =
   BITFIELD (VexOpcode),
   BITFIELD (VexSources),
   BITFIELD (VecSIB),
+  BITFIELD (VecSIBQword),
   BITFIELD (SSE2AVX),
   BITFIELD (NoAVX),
   BITFIELD (EVex),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 1516dd96b4..7d5f685322 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -538,6 +538,11 @@ enum
 #define VecSIB256	2
 #define VecSIB512	3
   VecSIB,
+  /* Instruction with vector SIB byte:
+	0: Dword indices.
+	1: Qword indices.
+   */
+  VecSIBQword,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
@@ -661,6 +666,7 @@ typedef struct i386_opcode_modifier
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int vecsib:2;
+  unsigned int vecsibqword:1;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int evex:3;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 1194dcd1c0..1518992ac0 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2389,18 +2389,18 @@ vgatherdpd, 3, 0x6692, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|
 vgatherdpd, 3, 0x6692, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
 vgatherdps, 3, 0x6692, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
 vgatherdps, 3, 0x6692, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
-vgatherqpd, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
-vgatherqpd, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
-vgatherqps, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vgatherqps, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vgatherqpd, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=1, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
+vgatherqpd, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=2, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vgatherqps, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vgatherqps, 3, 0x6693, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=2, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
 vpgatherdd, 3, 0x6690, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
 vpgatherdd, 3, 0x6690, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
 vpgatherdq, 3, 0x6690, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
 vpgatherdq, 3, 0x6690, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
-vpgatherqd, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherqd, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherqq, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=1, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
-vpgatherqq, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB=2, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
+vpgatherqd, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=1, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherqd, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=2, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherqq, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=1, { RegXMM, Qword|Unspecified|BaseIndex, RegXMM }
+vpgatherqq, 3, 0x6691, None, 1, CpuAVX2, Modrm|Vex=2|VexOpcode=1|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIBQword|VecSIB=2, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
 
 // AES + AVX
 
@@ -3373,9 +3373,9 @@ vpcompressq, 2, 0x668B, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=1|VexW=
 vpcompressd, 2, 0x668B, None, 1, CpuAVX512F, Modrm|MaskingMorZ|VexOpcode=1|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex }
 
 vpscatterdq, 2, 0x66A0, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
-vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
+vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
 vscatterdpd, 2, 0x66A2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
-vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
+vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
 
 vpscatterdd, 2, 0x66A0, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
 vscatterdps, 2, 0x66A2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex }
@@ -3636,16 +3636,16 @@ vscalefss, 3, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=1|Ve
 vscalefss, 4, 0x662D, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
 
 vgatherdpd, 2, 0x6692, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
-vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
+vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
 vpgatherdq, 2, 0x6690, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
-vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
+vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM }
 
 vgatherdps, 2, 0x6692, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM }
 vmovntdqa, 2, 0x662A, None, 1, CpuAVX512F, Modrm|VexOpcode=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM }
 
-vgatherqps, 2, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
-vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
+vgatherqps, 2, 0x6693, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
+vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
 
 vgetexppd, 2, 0x6642, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vgetexppd, 3, 0x6642, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegZMM }
@@ -3868,8 +3868,8 @@ vprord, 3, 0x6672, 0, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=2|VexW=
 vprolq, 3, 0x6672, 1, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 vprorq, 3, 0x6672, 0, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexVVVV=2|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
-vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
-vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
+vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
+vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
 
 vpshufd, 3, 0x6670, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
@@ -3957,22 +3957,22 @@ vrsqrt28ss, 4, 0x66CD, None, 1, CpuAVX512ER, Modrm|EVex=4|Masking=3|VexOpcode=1|
 // AVX512PF instructions.
 
 vgatherpf0dpd, 1, 0x66C6, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
-vgatherpf0qpd, 1, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
+vgatherpf0qpd, 1, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
 vgatherpf1dpd, 1, 0x66C6, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
-vgatherpf1qpd, 1, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
+vgatherpf1qpd, 1, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
 vscatterpf0dpd, 1, 0x66C6, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
-vscatterpf0qpd, 1, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
+vscatterpf0qpd, 1, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
 vscatterpf1dpd, 1, 0x66C6, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
-vscatterpf1qpd, 1, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
+vscatterpf1qpd, 1, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex }
 
 vgatherpf0dps, 1, 0x66C6, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
-vgatherpf0qps, 1, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
+vgatherpf0qps, 1, 0x66C7, 1, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
 vgatherpf1dps, 1, 0x66C6, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
-vgatherpf1qps, 1, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
+vgatherpf1qps, 1, 0x66C7, 2, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
 vscatterpf0dps, 1, 0x66C6, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
-vscatterpf0qps, 1, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
+vscatterpf0qps, 1, 0x66C7, 5, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
 vscatterpf1dps, 1, 0x66C6, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
-vscatterpf1qps, 1, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
+vscatterpf1qps, 1, 0x66C7, 6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex }
 
 // AVX512PF instructions end.
 
@@ -4015,34 +4015,34 @@ enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_l
 // AVX512VL instructions.
 
 vgatherdpd, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
+vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
+vgatherqpd, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
 vpgatherdq, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
-vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
+vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
+vpgatherqq, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
 vpscatterdq, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex }
-vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
+vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+vpscatterqq, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
 vscatterdpd, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex }
-vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
+vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex }
+vscatterqpd, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=2|Disp8MemShift=3|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex }
 
 vgatherdps, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
 vgatherdps, 2, 0x6692, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
-vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vgatherqps, 2, 0x6693, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
 vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
 vpgatherdd, 2, 0x6690, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM }
-vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
-vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
+vpgatherqd, 2, 0x6691, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM }
 vpscatterdd, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
 vpscatterdd, 2, 0x66A0, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
-vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
-vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vpscatterqd, 2, 0x66A1, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
 vscatterdps, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
 vscatterdps, 2, 0x66A2, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex }
-vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
-vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
+vscatterqps, 2, 0x66A3, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|VexOpcode=1|VexW=1|Disp8MemShift=2|VecSIBQword|VecSIB=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex }
 
 vcvtdq2pd, 2, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|Masking=3|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegYMM }
 vcvtdq2pd, 2, 0xF3E6, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Broadcast|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex, RegXMM }

Follow-Ups:
- Re: V3: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich

References:
- [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich

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