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V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base

From: "H.J. Lu" <hjl dot tools at gmail dot com>
To: Jan Beulich <JBeulich at suse dot com>, Binutils <binutils at sourceware dot org>
Date: Mon, 25 Feb 2019 20:35:08 -0800
Subject: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
References: <20190225140212.7737-1-hjl.tools@gmail.com> <5C74064C0200007800219F31@prv1-mh.provo.novell.com> <CAMe9rOr08jU4Pi6OjuqqbLYC+c513Ky-DR_F+1cCn6UcyJEg=A@mail.gmail.com> <5C741560020000780021A002@prv1-mh.provo.novell.com> <CAMe9rOofzOj=LAZ9h6q0C5=0TsWw2SM3oifiq1VukkczZD7tRg@mail.gmail.com> <CAMe9rOpss_CcbYr0_dm2Jccf03TbifSY=W1JKKYs0k1+tftT-Q@mail.gmail.com>
On Mon, Feb 25, 2019 at 02:54:28PM -0800, H.J. Lu wrote:
> Here is the updated patch.  Tested for glibc, GCC, binutils and CPU
> CPU 2000.
> 

This patch changed error into warning for GCC.


H.J.
---
In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address without base
register so that vector index register will be zero-extended to 64 bits.

We can't have ADDR_PREFIX_OPCODE prefix with 32-bit address if there is
segment override since address will be segment base + zero-extended to 64
bits of (base + index * scale + disp).  But GCC:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89502

generates

	movl	$24, %edx
	movl	%fs:(%edx), %ecx

instead of

	movl	%fs:24, %ecx

So a warning:

Warning: segment `%fs' override with 32-bit address

is issued by default.  -moperand-check=error will turn a warning into
an error.

Error: can't encode segment `%fs' with 32-bit address

	PR gas/24263
	* config/tc-i386.c (output_insn): In x32, add 0x67 address size
	prefix for VSIB address without base register.  Issue a warning
	or an error if there is segment override with ADDR_PREFIX_OPCODE
	prefix.
	* testsuite/gas/i386/ilp32/ilp32.exp: Run x86-64-seg-inval.
	* testsuite/gas/i386/ilp32/x86-64-seg-inval.l: New file.
	* testsuite/gas/i386/ilp32/x86-64-seg-inval.s: Likewise.
	* estsuite/gas/i386/ilp32/x86-64-seg-warn.d: Likewise.
	* estsuite/gas/i386/ilp32/x86-64-seg-warn.s: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg.d: Likewise.
	* testsuite/gas/i386/ilp32/x86-64-seg.s: Likewise.
---
 gas/config/tc-i386.c                          |  30 +++
 gas/testsuite/gas/i386/ilp32/ilp32.exp        |   1 +
 .../gas/i386/ilp32/x86-64-seg-inval.l         |   7 +
 .../gas/i386/ilp32/x86-64-seg-inval.s         |   9 +
 .../gas/i386/ilp32/x86-64-seg-warn.d          |  17 ++
 .../gas/i386/ilp32/x86-64-seg-warn.e          |   7 +
 gas/testsuite/gas/i386/ilp32/x86-64-seg.d     | 207 ++++++++++++++++++
 gas/testsuite/gas/i386/ilp32/x86-64-seg.s     |   9 +
 8 files changed, 287 insertions(+)
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.d
 create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d31ee6abdd..df7c152cc4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8141,6 +8141,36 @@ output_insn (void)
 	  i.prefix[LOCK_PREFIX] = 0;
 	}
 
+#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
+      if (flag_code == CODE_64BIT && x86_elf_abi == X86_64_X32_ABI)
+	{
+	  /* In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address
+	     without base register so that vector index register will
+	     be zero-extended to 64 bits.  */
+	  if (!i.base_reg && i.tm.opcode_modifier.vecsib)
+	    add_prefix (ADDR_PREFIX_OPCODE);
+	  /* In x32, we can't have ADDR_PREFIX_OPCODE prefix with
+	     segment override since final address will be segment
+	     base + zero-extended (base + index * scale + disp).  */
+	  if (operand_check != check_none
+	      && i.prefix[ADDR_PREFIX]
+	      && i.prefix[SEG_PREFIX])
+	    {
+	      const seg_entry *seg;
+	      if (i.seg[0])
+		seg = i.seg[0];
+	      else
+		seg = i.seg[1];
+	      if (operand_check == check_error)
+		as_bad (_("can't encode segment `%s%s' with 32-bit address"),
+			register_prefix, seg->seg_name);
+	      else
+		as_warn (_("segment `%s%s' override with 32-bit address"),
+			 register_prefix, seg->seg_name);
+	    }
+	}
+#endif
+
       /* Since the VEX/EVEX prefix contains the implicit prefix, we
 	 don't need the explicit prefix.  */
       if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
diff --git a/gas/testsuite/gas/i386/ilp32/ilp32.exp b/gas/testsuite/gas/i386/ilp32/ilp32.exp
index d3a7190ac5..fe1e9ea5df 100644
--- a/gas/testsuite/gas/i386/ilp32/ilp32.exp
+++ b/gas/testsuite/gas/i386/ilp32/ilp32.exp
@@ -38,6 +38,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_x32_check] &
     }
 
     run_list_test "reloc64" "--defsym _bad_=1"
+    run_list_test "x86-64-seg-inval" "-moperand-check=error"
 
     set ASFLAGS "$old_ASFLAGS"
 }
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
new file mode 100644
index 0000000000..7ec3f4d14b
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:4: Error: can't encode segment `%fs' with 32-bit address
+.*:5: Error: can't encode segment `%gs' with 32-bit address
+.*:6: Error: can't encode segment `%fs' with 32-bit address
+.*:7: Error: can't encode segment `%fs' with 32-bit address
+.*:8: Error: can't encode segment `%gs' with 32-bit address
+.*:9: Error: can't encode segment `%gs' with 32-bit address
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
new file mode 100644
index 0000000000..8117c68ec2
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
@@ -0,0 +1,9 @@
+	.text
+	.allow_index_reg
+_start:
+	vgatherdps %ymm12,%fs:0xc(%eax,%ymm15,1),%ymm11
+	vgatherdps %ymm12,%gs:0xc(,%ymm15,1),%ymm11
+	movl	%fs:(%eax), %eax
+	movl	%fs:(,%eax,1), %eax
+	movl	%gs:(,%eiz,1), %eax
+	movl	%gs:(%eip), %eax
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
new file mode 100644
index 0000000000..7c317c2d6b
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.d
@@ -0,0 +1,17 @@
+#source: x86-64-seg-inval.s
+#warning_output: x86-64-seg-warn.e
+#objdump: -dw
+#name: x86-64 (ILP32) segment (warning)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	64 67 c4 22 1d 92 5c 38 0c 	vgatherdps %ymm12,%fs:0xc\(%eax,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	65 67 c4 22 1d 92 1c 3d 0c 00 00 00 	vgatherdps %ymm12,%gs:0xc\(,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	64 67 8b 00          	mov    %fs:\(%eax\),%eax
+ +[a-f0-9]+:	64 67 8b 04 05 00 00 00 00 	mov    %fs:0x0\(,%eax,1\),%eax
+ +[a-f0-9]+:	65 67 8b 04 25 00 00 00 00 	mov    %gs:0x0\(,%eiz,1\),%eax
+ +[a-f0-9]+:	65 67 8b 05 00 00 00 00 	mov    %gs:0x0\(%eip\),%eax        # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
new file mode 100644
index 0000000000..f5a030f220
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-warn.e
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:4: Warning: segment `%fs' override with 32-bit address
+.*:5: Warning: segment `%gs' override with 32-bit address
+.*:6: Warning: segment `%fs' override with 32-bit address
+.*:7: Warning: segment `%fs' override with 32-bit address
+.*:8: Warning: segment `%gs' override with 32-bit address
+.*:9: Warning: segment `%gs' override with 32-bit address
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
new file mode 100644
index 0000000000..86e5526676
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
@@ -0,0 +1,207 @@
+#as: -I$srcdir/$subdir
+#objdump: -dw
+#name: x86-64 (ILP32) segment
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+:	c4 e2 e9 92 4c 7d 00 	vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 93 4c 7d 00 	vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 92 4c 7d 00 	vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 93 4c 7d 00 	vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 92 5c 75 00 	vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 93 5c 75 00 	vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 92 5c 75 00 	vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 93 5c 75 00 	vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 69 92 4c 7d 00 	vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 92 4c 7d 00 	vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 92 5c 75 00 	vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 92 5c 75 00 	vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 69 90 4c 7d 00 	vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 90 4c 7d 00 	vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 90 5c 75 00 	vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 90 5c 75 00 	vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 e9 90 4c 7d 00 	vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 91 4c 7d 00 	vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 90 4c 7d 00 	vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 91 4c 7d 00 	vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 90 5c 75 00 	vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 91 5c 75 00 	vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 90 5c 75 00 	vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 91 5c 75 00 	vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 e9 92 4c 7d 00 	vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 93 4c 7d 00 	vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 92 4c 7d 00 	vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 93 4c 7d 00 	vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 92 5c 75 00 	vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 93 5c 75 00 	vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 92 5c 75 00 	vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 93 5c 75 00 	vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 25 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 92 34 e5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 35 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 08 00 00 00 	vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 f8 ff ff ff 	vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 00 00 00 00 	vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 92 34 f5 98 02 00 00 	vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	c4 e2 69 92 4c 7d 00 	vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 92 4c 7d 00 	vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 93 4c 7d 00 	vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 92 5c 75 00 	vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 92 5c 75 00 	vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 93 5c 75 00 	vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 25 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 92 34 e5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 35 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 08 00 00 00 	vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 f8 ff ff ff 	vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 00 00 00 00 	vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 92 34 f5 98 02 00 00 	vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 69 90 4c 7d 00 	vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 69 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 6d 90 4c 7d 00 	vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 6d 91 4c 7d 00 	vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+:	c4 02 19 90 5c 75 00 	vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 19 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 1d 90 5c 75 00 	vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 1d 91 5c 75 00 	vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 25 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 e2 51 90 34 e5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 35 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 08 00 00 00 	vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 f8 ff ff ff 	vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 00 00 00 00 	vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	67 c4 a2 51 90 34 f5 98 02 00 00 	vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+:	c4 e2 e9 90 4c 7d 00 	vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 e9 91 4c 7d 00 	vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+:	c4 e2 ed 90 4c 7d 00 	vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+:	c4 e2 ed 91 4c 7d 00 	vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+:	c4 02 99 90 5c 75 00 	vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 99 91 5c 75 00 	vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+:	c4 02 9d 90 5c 75 00 	vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+:	c4 02 9d 91 5c 75 00 	vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 25 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 e2 d5 90 34 e5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 35 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 08 00 00 00 	vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 f8 ff ff ff 	vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 00 00 00 00 	vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	67 c4 a2 d5 90 34 f5 98 02 00 00 	vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+:	64 8b 04 25 00 00 00 00 	mov    %fs:0x0,%eax
+ +[a-f0-9]+:	65 8b 05 00 00 00 00 	mov    %gs:0x0\(%rip\),%eax        # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+ +[a-f0-9]+:	65 8b 00             	mov    %gs:\(%rax\),%eax
+ +[a-f0-9]+:	67 c4 22 1d 92 5c 38 0c 	vgatherdps %ymm12,0xc\(%eax,%ymm15,1\),%ymm11
+ +[a-f0-9]+:	64 c4 22 1d 92 5c 38 0c 	vgatherdps %ymm12,%fs:0xc\(%rax,%ymm15,1\),%ymm11
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
new file mode 100644
index 0000000000..7ad33e498c
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
@@ -0,0 +1,9 @@
+.include "../x86-64-avx-gather.s"
+
+	.text
+	.att_syntax
+	movl	%fs:0, %eax
+	movl	%gs:(%rip), %eax
+	movl	%gs:(%rax), %eax
+	vgatherdps	%ymm12,0xc(%eax,%ymm15,1),%ymm11
+	vgatherdps	%ymm12,%fs:0xc(%rax,%ymm15,1),%ymm11
-- 
2.20.1
Follow-Ups:
- Re: V2: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
References:
- [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: Jan Beulich
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
- Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
  - From: H.J. Lu
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