This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
Re: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
On Mon, Feb 25, 2019 at 8:53 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Feb 25, 2019 at 8:18 AM Jan Beulich <JBeulich@suse.com> wrote:
> >
> > >>> On 25.02.19 at 16:55, <hjl.tools@gmail.com> wrote:
> > > On Mon, Feb 25, 2019 at 7:14 AM Jan Beulich <JBeulich@suse.com> wrote:
> > >>
> > >> >>> On 25.02.19 at 15:02, <hjl.tools@gmail.com> wrote:
> > >> > --- a/gas/config/tc-i386.c
> > >> > +++ b/gas/config/tc-i386.c
> > >> > @@ -8194,6 +8194,32 @@ output_insn (void)
> > >> > }
> > >> > else
> > >> > {
> > >> > +#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
> > >> > + if (x86_elf_abi == X86_64_X32_ABI
> > >> > + && i.tm.opcode_modifier.vecsib)
> > >> > + {
> > >> > + /* In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address
> > >> > + without base register so that vector index register
> > >> > + won't be sign-extended to 64 bits. */
> > >> > + if (!i.base_reg)
> > >> > + add_prefix (ADDR_PREFIX_OPCODE);
> > >>
> > >> Leaving aside the question of how one would go about overriding
> > >> this behavior (after all iirc it's not forbidden to use full 64-bit
> > >> addresses / base registers in x32) I understand this part, but ...
> > >
> > > You can use a 64-bit base register to avoid 0x67 prefix,
> >
> > I don't understand - this is about the no-base-register case. I was
> > referring to the 64-bit base register case merely for comparison
> > purposes. Don't forget that in the qword-index-element case you
> > now actively truncate index elements.
>
> Without a base register, 0x67 prefix will added for VSIB.
>
> > >> > + /* In x32, we can't have ADDR_PREFIX_OPCODE prefix for
> > >> > + VSIB if there is segment override since address will
> > >> > + be segment override + zero-extended to 64 bits of
> > >> > + (base + index * scale + disp). */
> > >>
> > >> ... I don't understand this: What is it that goes wrong here in
> > >> x32 mode? "base" is either zero or a full 64-bit value anyway, so
> > >
> > > "base" can be a 32-bit register:
> > >
> > > vgatherdps %ymm12,%fs:0xc(%eax,%ymm15,1),%ymm11
> >
> > Oh, sorry, I mixed up base and segment base (because of the
> > mention of a segment override here).
>
> Explicit segment is disallowed for 32-bit address in x32.
>
> > >> I'm struggling in the first place what (uniform) zero-extension the
> > >> comment is talking about. But I also don't understand why, if this
> > >> was needed at all, it would affect VSIB addressing only.
> > >
> > > Segment override is applied AFTER "base + index * scale + disp".
> > > So memory address in
> > >
> > > movl %fs:(%eax), %eax
> > >
> > > is %fs + zero-extend (%eax), not zero-extend (%fs + %eax).
> >
> > Sure.
> >
> > > In x32, GCC avoids 32-bit base/index for TLS:
> > >[...]
> >
> > I'm sorry, but this still doesn't make me see what's wrong with
> > segment overrides in x32 mode, and only with VSIB addressing.
>
> I will add check for other cases.
>
> > >> > + if (i.prefix[ADDR_PREFIX] && i.prefix[SEG_PREFIX])
> > >> > + {
> > >> > + const seg_entry *seg;
> > >> > + if (i.seg[0])
> > >> > + seg = i.seg[0];
> > >> > + else
> > >> > + seg = i.seg[1];
> > >> > + as_bad (_("can't encode segment `%s' with 32-bit VSIB"),
> > >> > + seg->seg_name);
> > >>
> > >> Please don't emit the % prefix unconditionally, it should not be there
> > >> in no-prefix / Intel mode.
> > >
> > > What % prefix?
> > >
> > > [hjl@gnu-4 pr24263]$ cat y.s
> > > .text
> > > vgatherdps %ymm12,%fs:0xc(%eax,%ymm15,1),%ymm11
> > > vgatherdps %ymm12,%fs:0xc(,%ymm15,1),%ymm11
> > > [hjl@gnu-4 pr24263]$ ./as --x32 -o y.o y.s
> > > y.s: Assembler messages:
> > > y.s:2: Error: can't encode segment `fs' with 32-bit VSIB
> > > y.s:3: Error: can't encode segment `fs' with 32-bit VSIB
> > > [hjl@gnu-4 pr24263]$
> >
> > Oops, sorry - I should have asked for a % prefix to be added outside
> > of no-prefix mode.
>
> Sure.
>
Here is the updated patch. Tested for glibc, GCC, binutils and CPU
CPU 2000.
--
H.J.
From 18abbd9770fb021195cd3950e4a1104de5158d1b Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Sun, 24 Feb 2019 18:38:33 -0800
Subject: [PATCH] x32: Generate 0x67 prefix for VSIB address without base
In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address without base
register so that vector index register will be zero-extended to 64 bits.
We can't have ADDR_PREFIX_OPCODE prefix with 32-bit address if there is
segment override since address will be segment base + zero-extended to 64
bits of (base + index * scale + disp).
PR gas/24263
* config/tc-i386.c (output_insn): In x32, add 0x67 address size
prefix for VSIB address without base register and issue an error
if there is segment override with ADDR_PREFIX_OPCODE prefix.
* testsuite/gas/i386/ilp32/ilp32.exp: Run x86-64-seg-inval.
* testsuite/gas/i386/ilp32/x86-64-seg-inval.l: New file.
* testsuite/gas/i386/ilp32/x86-64-seg-inval.s: Likewise.
* testsuite/gas/i386/ilp32/x86-64-seg.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-seg.s: Likewise.
---
gas/config/tc-i386.c | 24 ++
gas/testsuite/gas/i386/ilp32/ilp32.exp | 1 +
.../gas/i386/ilp32/x86-64-seg-inval.l | 7 +
.../gas/i386/ilp32/x86-64-seg-inval.s | 8 +
gas/testsuite/gas/i386/ilp32/x86-64-seg.d | 207 ++++++++++++++++++
gas/testsuite/gas/i386/ilp32/x86-64-seg.s | 9 +
6 files changed, 256 insertions(+)
create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.d
create mode 100644 gas/testsuite/gas/i386/ilp32/x86-64-seg.s
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d31ee6abdd..7f53441a38 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8141,6 +8141,30 @@ output_insn (void)
i.prefix[LOCK_PREFIX] = 0;
}
+#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
+ if (flag_code == CODE_64BIT && x86_elf_abi == X86_64_X32_ABI)
+ {
+ /* In x32, add ADDR_PREFIX_OPCODE prefix for VSIB address
+ without base register so that vector index register will
+ be zero-extended to 64 bits. */
+ if (!i.base_reg && i.tm.opcode_modifier.vecsib)
+ add_prefix (ADDR_PREFIX_OPCODE);
+ /* In x32, we can't have ADDR_PREFIX_OPCODE prefix with
+ segment override since final address will be segment
+ base + zero-extended (base + index * scale + disp). */
+ if (i.prefix[ADDR_PREFIX] && i.prefix[SEG_PREFIX])
+ {
+ const seg_entry *seg;
+ if (i.seg[0])
+ seg = i.seg[0];
+ else
+ seg = i.seg[1];
+ as_bad (_("can't encode segment `%s%s' with 32-bit address"),
+ register_prefix, seg->seg_name);
+ }
+ }
+#endif
+
/* Since the VEX/EVEX prefix contains the implicit prefix, we
don't need the explicit prefix. */
if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
diff --git a/gas/testsuite/gas/i386/ilp32/ilp32.exp b/gas/testsuite/gas/i386/ilp32/ilp32.exp
index d3a7190ac5..eba03ae891 100644
--- a/gas/testsuite/gas/i386/ilp32/ilp32.exp
+++ b/gas/testsuite/gas/i386/ilp32/ilp32.exp
@@ -38,6 +38,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_x32_check] &
}
run_list_test "reloc64" "--defsym _bad_=1"
+ run_list_test "x86-64-seg-inval"
set ASFLAGS "$old_ASFLAGS"
}
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
new file mode 100644
index 0000000000..be11a408df
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:3: Error: can't encode segment `%fs' with 32-bit address
+.*:4: Error: can't encode segment `%gs' with 32-bit address
+.*:5: Error: can't encode segment `%fs' with 32-bit address
+.*:6: Error: can't encode segment `%fs' with 32-bit address
+.*:7: Error: can't encode segment `%gs' with 32-bit address
+.*:8: Error: can't encode segment `%gs' with 32-bit address
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
new file mode 100644
index 0000000000..c5097e7cab
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg-inval.s
@@ -0,0 +1,8 @@
+ .text
+ .allow_index_reg
+ vgatherdps %ymm12,%fs:0xc(%eax,%ymm15,1),%ymm11
+ vgatherdps %ymm12,%gs:0xc(,%ymm15,1),%ymm11
+ movl %fs:(%eax), %eax
+ movl %fs:(,%eax,1), %eax
+ movl %gs:(,%eiz,1), %eax
+ movl %gs:(%eip), %eax
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.d b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
new file mode 100644
index 0000000000..86e5526676
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.d
@@ -0,0 +1,207 @@
+#as: -I$srcdir/$subdir
+#objdump: -dw
+#name: x86-64 (ILP32) segment
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+ +[a-f0-9]+: c4 e2 e9 92 4c 7d 00 vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 e9 93 4c 7d 00 vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 ed 92 4c 7d 00 vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 ed 93 4c 7d 00 vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 02 99 92 5c 75 00 vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 99 93 5c 75 00 vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 9d 92 5c 75 00 vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 9d 93 5c 75 00 vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: c4 e2 69 92 4c 7d 00 vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 69 93 4c 7d 00 vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 6d 92 4c 7d 00 vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 6d 93 4c 7d 00 vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+: c4 02 19 92 5c 75 00 vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 19 93 5c 75 00 vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 1d 92 5c 75 00 vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 1d 93 5c 75 00 vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: c4 e2 69 90 4c 7d 00 vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 69 91 4c 7d 00 vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 6d 90 4c 7d 00 vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 6d 91 4c 7d 00 vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+: c4 02 19 90 5c 75 00 vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 19 91 5c 75 00 vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 1d 90 5c 75 00 vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 1d 91 5c 75 00 vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: c4 e2 e9 90 4c 7d 00 vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 e9 91 4c 7d 00 vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 ed 90 4c 7d 00 vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 ed 91 4c 7d 00 vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 02 99 90 5c 75 00 vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 99 91 5c 75 00 vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 9d 90 5c 75 00 vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 9d 91 5c 75 00 vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: c4 e2 e9 92 4c 7d 00 vgatherdpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 e9 93 4c 7d 00 vgatherqpd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 ed 92 4c 7d 00 vgatherdpd %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 ed 93 4c 7d 00 vgatherqpd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 02 99 92 5c 75 00 vgatherdpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 99 93 5c 75 00 vgatherqpd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 9d 92 5c 75 00 vgatherdpd %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 9d 93 5c 75 00 vgatherqpd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 25 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 92 34 e5 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 35 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 08 00 00 00 vgatherdpd %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 f8 ff ff ff vgatherdpd %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 00 00 00 00 vgatherdpd %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 92 34 f5 98 02 00 00 vgatherdpd %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: c4 e2 69 92 4c 7d 00 vgatherdps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 69 93 4c 7d 00 vgatherqps %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 6d 92 4c 7d 00 vgatherdps %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 6d 93 4c 7d 00 vgatherqps %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+: c4 02 19 92 5c 75 00 vgatherdps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 19 93 5c 75 00 vgatherqps %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 1d 92 5c 75 00 vgatherdps %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 1d 93 5c 75 00 vgatherqps %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 25 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 92 34 e5 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 35 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 08 00 00 00 vgatherdps %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 f8 ff ff ff vgatherdps %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 00 00 00 00 vgatherdps %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 92 34 f5 98 02 00 00 vgatherdps %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: c4 e2 69 90 4c 7d 00 vpgatherdd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 69 91 4c 7d 00 vpgatherqd %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 6d 90 4c 7d 00 vpgatherdd %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 6d 91 4c 7d 00 vpgatherqd %xmm2,0x0\(%rbp,%ymm7,2\),%xmm1
+ +[a-f0-9]+: c4 02 19 90 5c 75 00 vpgatherdd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 19 91 5c 75 00 vpgatherqd %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 1d 90 5c 75 00 vpgatherdd %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 1d 91 5c 75 00 vpgatherqd %xmm12,0x0\(%r13,%ymm14,2\),%xmm11
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 25 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm4,1\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 e2 51 90 34 e5 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm4,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 35 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm14,1\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 08 00 00 00 vpgatherdd %xmm5,0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 f8 ff ff ff vpgatherdd %xmm5,-0x8\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 00 00 00 00 vpgatherdd %xmm5,0x0\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: 67 c4 a2 51 90 34 f5 98 02 00 00 vpgatherdd %xmm5,0x298\(,%xmm14,8\),%xmm6
+ +[a-f0-9]+: c4 e2 e9 90 4c 7d 00 vpgatherdq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 e9 91 4c 7d 00 vpgatherqq %xmm2,0x0\(%rbp,%xmm7,2\),%xmm1
+ +[a-f0-9]+: c4 e2 ed 90 4c 7d 00 vpgatherdq %ymm2,0x0\(%rbp,%xmm7,2\),%ymm1
+ +[a-f0-9]+: c4 e2 ed 91 4c 7d 00 vpgatherqq %ymm2,0x0\(%rbp,%ymm7,2\),%ymm1
+ +[a-f0-9]+: c4 02 99 90 5c 75 00 vpgatherdq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 99 91 5c 75 00 vpgatherqq %xmm12,0x0\(%r13,%xmm14,2\),%xmm11
+ +[a-f0-9]+: c4 02 9d 90 5c 75 00 vpgatherdq %ymm12,0x0\(%r13,%xmm14,2\),%ymm11
+ +[a-f0-9]+: c4 02 9d 91 5c 75 00 vpgatherqq %ymm12,0x0\(%r13,%ymm14,2\),%ymm11
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 25 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm4,1\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 e2 d5 90 34 e5 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm4,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 35 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm14,1\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 08 00 00 00 vpgatherdq %ymm5,0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 f8 ff ff ff vpgatherdq %ymm5,-0x8\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 00 00 00 00 vpgatherdq %ymm5,0x0\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 67 c4 a2 d5 90 34 f5 98 02 00 00 vpgatherdq %ymm5,0x298\(,%xmm14,8\),%ymm6
+ +[a-f0-9]+: 64 8b 04 25 00 00 00 00 mov %fs:0x0,%eax
+ +[a-f0-9]+: 65 8b 05 00 00 00 00 mov %gs:0x0\(%rip\),%eax # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+ +[a-f0-9]+: 65 8b 00 mov %gs:\(%rax\),%eax
+ +[a-f0-9]+: 67 c4 22 1d 92 5c 38 0c vgatherdps %ymm12,0xc\(%eax,%ymm15,1\),%ymm11
+ +[a-f0-9]+: 64 c4 22 1d 92 5c 38 0c vgatherdps %ymm12,%fs:0xc\(%rax,%ymm15,1\),%ymm11
+#pass
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-seg.s b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
new file mode 100644
index 0000000000..7ad33e498c
--- /dev/null
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-seg.s
@@ -0,0 +1,9 @@
+.include "../x86-64-avx-gather.s"
+
+ .text
+ .att_syntax
+ movl %fs:0, %eax
+ movl %gs:(%rip), %eax
+ movl %gs:(%rax), %eax
+ vgatherdps %ymm12,0xc(%eax,%ymm15,1),%ymm11
+ vgatherdps %ymm12,%fs:0xc(%rax,%ymm15,1),%ymm11
--
2.20.1