Re: patch r5900/micromips handling

[Richard Sandiford <rdsandiford at googlemail dot com>]

"JÃrgen Urban" <JuergenUrban@gmx.de> writes:
>> Looks good, thanks.  Just a couple of minor things:
>> 
>> "JÃrgen Urban" <JuergenUrban@gmx.de> writes:
>> > +/* True, if CPU has support for ldc1 and sdc1. */
>> > +#define CPU_HAS_LDC1_SDC1(CPU)	((mips_opts.isa != ISA_MIPS1) && ((CPU)
>> != CPU_R5900))
>> > +
>> 
>> Formatting, should be:
>> 
>> #define CPU_HAS_LDC1_SDC1(CPU) \
>>   (mips_opts.isa != ISA_MIPS1 && (CPU) != CPU_R5900)
>> 
>> 
>> >  /* True if mflo and mfhi can be immediately followed by instructions
>> >     which write to the HI and LO registers.
>> >  
>> > @@ -9027,8 +9030,7 @@ macro (struct mips_cl_insn *ip)
>> >        s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
>> >        if (strcmp (s, ".lit8") == 0)
>> >  	{
>> > -	  if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips)
>> > -	    && (mips_opts.arch != CPU_R5900))
>> > +	  if (CPU_HAS_LDC1_SDC1(mips_opts.arch) || mips_opts.micromips)
>> 
>> Missing space before "(".  A few other cases.
>> 
>> > diff -Nurp
>> binutils-cvs-20130104/gas/testsuite/gas/mips/24k-triple-stores-2.s
>> binutils-cvs-20130104-mips64el-linux-patched/gas/testsuite/gas/mips/24k-triple-stores-2.s
>> > ---
>> binutils-cvs-20130104/gas/testsuite/gas/mips/24k-triple-stores-2.s
>> 2013-01-26 18:28:08.503235967 +0100
>> > +++
>> binutils-cvs-20130104-mips64el-linux-patched/gas/testsuite/gas/mips/24k-triple-stores-2.s
>> 2013-01-26 21:08:44.343223485 +0100
>> > @@ -28,12 +28,6 @@ foo:
>> >  	swl      $6,0($sp)
>> >  	break
>> >  
>> > -	sc      $2,32($sp)
>> > -	sc      $3,8($sp)
>> > -	sc      $4,-8($sp)
>> > -	sc      $5,0($sp)
>> > -	sc      $6,32($sp)
>> > -
>> 
>> Please remove the last "break" too, since it was there to separate
>> groups of stores.
>
> It is now fixed. The attached patch can be applied without the previous
> VU0 patch. ragnarok2040 will need more time fix the VU0 patch.

Applied with the ChangeLog below, thanks.

For the record, I added -EL to the l_d-single and s_d-single options,
so that the tests wouldn't fail on big-endian targets like mips64-elf.
I also used o64 rather than n32 so that the tests wouuldn't fail
on *-elf (as opposed to *-linux-gnu) targets.

The l_d-single and s_d-single tests didn't pass for mips-ecoff, but frankly
who knows whether the output we get there is correct or not.  Rather than
codify something that might not be right, I just restricted the tests to
ELF and removed the RELLO, RELHI and GPREL stuff.

Thanks again for working on this.

Richard


gas/
2013-02-09  JÃrgen Urban  <JuergenUrban@gmx.de>

	* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
	(macro): Use it.  Assert that trunc.w.s is not used for r5900.

opcodes/
2013-02-09  JÃrgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
	trunc.w.s macro for EE.

gas/testsuite/
2013-02-09  JÃrgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
	gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
	* gas/mips/24k-triple-stores-2-llsc.d,
	gas/mips/24k-triple-stores-2-llsc.s,
	gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
	* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
	MIPS ISA level can be upgraded to support ll, sc, lld and scd.
	* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
	gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
	* gas/mips/mips.exp: Update accordingly.  Add "nollsc" to r5900
	properties.