[PATCH v1 2/3] riscv: Add RVV implementation __strcpy_vector

[Jeff Law]

On 9/18/25 18:50, Yao Zihong wrote:
> This patch adds the RVV-optimized __strcpy_vector implementation and builds
> it, but does not wire it up via IFUNC nor resolver yet.
> 
> - Add sysdeps/riscv/multiarch/strcpy_vector.S for RVV implementation __strcpy_vector.
> - Register __strcpy_vector in the multiarch Makefile.
So this is considerably more complex than what we've been using.  Ours 
is just:

> +L(strcpy_loop):
> +    vsetvli ivl, zero, e8, ELEM_LMUL_SETTING, ta, ma
> +    vle8ff.v vstr1, (src)
> +    vmseq.vx vmask2, vstr1, zero
> +    csrr cur_vl, vl
> +    vfirst.m active_elem_pos, vmask2
> +    vmsif.m vmask1, vmask2
> +    add src, src, cur_vl
> +    vse8.v vstr1, (dst_ptr), vmask1.t
> +    add dst_ptr, dst_ptr, cur_vl
> +    bltz active_elem_pos, L(strcpy_loop)

I would want to lean more towards the simpler implementation until such 
time as we know if unrolled versions and such are actually profitable on 
multiple micro-architectures.

The worry is the conditional branches in yours are going to miss 
relatively often with a significant penalty and that penalty will only 
get larger on more aggressive cores than what's found in the spacemit 
design.


Did you happen to performance test a simpler version before you went to 
the more complex implementation?

Jeff