[PATCH v1 2/3] riscv: Add RVV implementation __strcpy_vector

[Yao Zihong]

This patch adds the RVV-optimized __strcpy_vector implementation and builds
it, but does not wire it up via IFUNC nor resolver yet.

- Add sysdeps/riscv/multiarch/strcpy_vector.S for RVV implementation __strcpy_vector.
- Register __strcpy_vector in the multiarch Makefile.

Signed-off-by: Yao Zihong <zihong.plct@isrc.iscas.ac.cn>
---
 sysdeps/riscv/multiarch/strcpy_vector.S       | 89 +++++++++++++++++++
 .../unix/sysv/linux/riscv/multiarch/Makefile  |  1 +
 2 files changed, 90 insertions(+)
 create mode 100644 sysdeps/riscv/multiarch/strcpy_vector.S

diff --git a/sysdeps/riscv/multiarch/strcpy_vector.S b/sysdeps/riscv/multiarch/strcpy_vector.S
new file mode 100644
index 0000000000..f28840dfcb
--- /dev/null
+++ b/sysdeps/riscv/multiarch/strcpy_vector.S
@@ -0,0 +1,89 @@
+/* strcpy for RISC-V, vectorized version
+   Copyright (C) 2025 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library.  If not, see
+   <https://www.gnu.org/licenses/>.  */
+
+#include <sysdep.h>
+#include <sys/asm.h>
+
+# define pDst		a0
+# define pSrc		a1
+# define pDstPtr	a2
+
+# define iVL		a3
+# define iVlMask	a4
+# define iActPos	a5
+# define iSrcAlign	a6
+
+# define vMask		v0
+# define vStr		v4
+
+ENTRY (__strcpy_vector)
+.option push
+.option arch, +v
+	mv		pDstPtr, pDst
+
+	vsetvli		iVL, zero, e8, m1, ta, ma
+	vle8ff.v	vStr, (pSrc)
+
+	vmseq.vx	vMask, vStr, zero
+	vfirst.m	iActPos, vMask
+	bgez		iActPos, L(m1_vector_exit)
+
+	vse8.v		vStr, (pDstPtr)
+	csrr		iVL, vl
+	add		pSrc, pSrc, iVL
+	add		pDstPtr, pDstPtr, iVL
+
+	vsetvli		iVL, zero, e8, m4, ta, ma
+	vle8ff.v	vStr, (pSrc)
+	
+	vmseq.vx	vMask, vStr, zero
+	vfirst.m	iActPos, vMask
+	bgez		iActPos, L(m4_vector_exit)
+
+	addi		iVlMask, iVL, -1
+	vse8.v		vStr, (pDstPtr)
+	vsetvli		zero, zero, e8, m4, ta, ma
+	and		iSrcAlign, pSrc, iVlMask
+	add		pSrc, pSrc, iVL
+	add		pDstPtr, pDstPtr, iVL
+	sub		pSrc, pSrc, iSrcAlign
+	sub		pDstPtr, pDstPtr, iSrcAlign
+L(m4_vector_loop):
+	vle8.v		vStr, (pSrc)
+
+	vmseq.vx	vMask, vStr, zero
+	vfirst.m	iActPos, vMask
+	bltz		iActPos, L(m4_vector_store)
+L(m4_vector_exit):
+	addi		iActPos, iActPos, 1
+	vsetvli		x0, iActPos, e8, m4, ta, ma
+	vse8.v		vStr, (pDstPtr)
+	ret
+L(m4_vector_store):
+	vse8.v		vStr, (pDstPtr)
+	add		pSrc, pSrc, iVL
+	add		pDstPtr, pDstPtr, iVL
+	j		L(m4_vector_loop)
+L(m1_vector_exit):
+	addi		iActPos, iActPos, 1
+	vsetvli		x0, iActPos, e8, m1, ta, ma
+	vse8.v		vStr, (pDstPtr)
+	ret
+.option pop
+END(__strcpy_vector)
+libc_hidden_builtin_def (__strcpy_vector)
diff --git a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile
index b1c6d702c2..da3b55c5c4 100644
--- a/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile
+++ b/sysdeps/unix/sysv/linux/riscv/multiarch/Makefile
@@ -5,6 +5,7 @@ sysdep_routines += \
   memcpy_noalignment \
   strcpy \
   strcpy-generic \
+  strcpy_vector \
   # sysdep_routines
 
 CFLAGS-memcpy_noalignment.c += -mno-strict-align
-- 
2.47.2