[PATCH v3 1/1] riscv: Add RVV memset via multiarch/IFUNC

[Yao Zihong]

Hi Darius,

Would this address the concern?

> Currently, the resolver still selects the RVV variant even when the
> extension has been disabled via prctl(). As a consequence, any process
> that disables RVV via prctl() will receive SIGILL when executing the
> first vector instruction.

Thanks,
Zihong