[PATCH v2 1/1] riscv: Add RVV memset via multiarch/IFUNC

[Adhemerval Zanella Netto]

On 04/11/25 11:33, Darius Rad wrote:
> On Tue, Nov 04, 2025 at 08:37:49PM +0800, Yao Zihong wrote:
>> This patch adds an RVV-optimized implementation of memset for RISC-V and
>> enables it through the existing multiarch/IFUNC mechanism.
>>
>> The implementation integrates Hau Hsu’s 2023 RVV work under a unified
>> ifunc-based framework. A vectorized version (__memset_vector) is added
>> alongside the generic fallback (__memset_generic). The runtime resolver
>> selects the RVV variant when RISCV_HWPROBE_KEY_IMA_EXT_0 reports vector
>> support (V).
> 
> This needs to use dl_hwcap, as I said before [1].
> 
> [1] https://sourceware.org/pipermail/libc-alpha/2025-October/171687.html
> 
>>
>> Tested on MUSE-Pi (SpacemiT M1) and verified by Jeff Law on BPI and
>> Pioneer boards with no regressions compared with glibc master.
> 
> This patch certainly has regressions compared with glibc master.
> Presently, if one has an environment that implements the vector extension,
> but it is disabled at runtime with prctl, glibc will operate properly.
> After this patch, running in such an environment will trigger an illegal
> instruction fault whenever memset is run.
> 

How do you propose to fix PR_RISCV_V_VSTATE_CTRL_OFF for function 
multiversioning [1]? Last time I checked libgcc only uses risc_hwprobes [2] 
to do the function selection.

There is also all __riscv_hwprobe consumers that might only assume it as the
authoritative source of hardware support.

[1] http://gcc.gnu.org/onlinedocs/gcc/Function-Multiversioning.html
[2] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=libgcc/config/riscv/feature_bits.c;h=157bcdcad69a939037f6faca3a90c2598dd61f89;hb=HEAD