[PATCH v2 1/1] riscv: Add RVV memset via multiarch/IFUNC

[Darius Rad]

On Tue, Nov 04, 2025 at 08:37:49PM +0800, Yao Zihong wrote:
> This patch adds an RVV-optimized implementation of memset for RISC-V and
> enables it through the existing multiarch/IFUNC mechanism.
> 
> The implementation integrates Hau Hsu’s 2023 RVV work under a unified
> ifunc-based framework. A vectorized version (__memset_vector) is added
> alongside the generic fallback (__memset_generic). The runtime resolver
> selects the RVV variant when RISCV_HWPROBE_KEY_IMA_EXT_0 reports vector
> support (V).

This needs to use dl_hwcap, as I said before [1].

[1] https://sourceware.org/pipermail/libc-alpha/2025-October/171687.html

> 
> Tested on MUSE-Pi (SpacemiT M1) and verified by Jeff Law on BPI and
> Pioneer boards with no regressions compared with glibc master.

This patch certainly has regressions compared with glibc master.
Presently, if one has an environment that implements the vector extension,
but it is disabled at runtime with prctl, glibc will operate properly.
After this patch, running in such an environment will trigger an illegal
instruction fault whenever memset is run.