[PATCH v5 1/1] riscv: Add RVV memset for both multiarch and non-multiarch builds

[Yao Zihong]

On Wed, 17 Dec 2025 20:45:03 -0700, Jeff Law wrote:
> Yao, which ones do you want to concentrate on next?  I'm happy to pass 
> along the generic implementations we have here.  Though if you've 
> already got them it may not be worth the effort.  Ours are a 
> run-of-the-mill RVV impementation without any meaningful tuning.

We've been exploring several of the mem*/str* routines based on Hau
Hsu's earlier series [1], mostly focusing on cleanup and small
adjustments (e.g. zca-friendliness). So far the gains are fairly modest.

For memrchr/strrchr in particular, one thing we've been exploring is the
use of v.id in e8 mode. That effectively caps the index range at 0-255,
which pushes us toward handling at most 256 bytes per iteration. We also
tried walking backwards with negative strides, but that performed poorly
in glibc benchmarks on the hardware we have (SpacemiT M1 and K230). It's
not clear yet whether that's more of an architectural effect or just our
current approach.

So it'd be great to compare notes with your generic implementations.

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[1] https://inbox.sourceware.org/libc-alpha/20230504074851.38763-1-hau.hsu@sifive.com/

Thanks,
Zihong