Disable 64-bit atomics for MIPS n32 [committed]

[Chris Metcalf]

On 1/28/2015 4:31 PM, Torvald Riegel wrote:
> On Wed, 2015-01-28 at 18:45 +0000, Joseph Myers wrote:
>> This patch disables use of 64-bit atomics for MIPS n32 to fix the
>> problems with unaligned semaphores.
> That works.  I would probably preferred to just do this in the semaphore
> bits (ie, checking for __HAVE_64B_ATOMICS and _LP64, but both have the
> same effect for 2.21.

You would then have disabled 64-bit atomics for x32, which may not
be the solution preferred by H.J.

>> Before 64-bit atomics are used for anything for which such alignment
>> issues do not arise, and before the addition of any new ILP32 ports
>> with 64-bit semaphores for which the ABI can be set to have the
>> greater alignment (AARCH64?), a better approach will need to be
>> established that allows architectures to declare their 64-bit atomics
>> availability accurately, without doing so causing inappropriate use of
>> such atomics on unaligned semaphores.
> I guess I'll have to add another flag for whether 64B atomics need to be
> naturally aligned or not.  I'm not yet sure how to express this best, so
> suggestions are welcome.  If we can say (for now) that we only support
> ILP32 and LP64, this might clarify the options we have -- I suspect that
> in most cases where 64B atomics will be useful, this will be for legacy
> code.
>
> OTOH, I'm not sure whether non-naturally-aligned 64B atomics actually
> really help us anywhere.  So we could as well just require them to be
> naturally aligned, and use _LP64 to check whether alignment for legacy
> code is sufficient.

Yes, requiring self-size-alignment for atomics would be my vote.
It's basically always the right thing to do, whether for performance
or correctness reasons.

I'm suspect all of the glibc ports are either ILP32 or LP64, by the way;
do you know of any that are not?

-- 
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com