non-decr_pc_after_break i386 targets

[Andrew Cagney]

> While reading the Solaris proc(4) man page I noticed the PR_BPTADJ
> flag.  If this flag is set, Solaris x86 "will adjust the program
> counter back to location of the breakpointed instructions when the lwp
> stops on a breakpoint".  The man page explicitly says that on SPARC
> this is a no-op.  Using this flag makes it possible to turn
> i386-*-solaris2* into an architecture where decr_pc_after_break is
> zero.  This would have remove some of the problems with breakpoints in
> signal trampolines on Solaris x86.  So I think we should do that.
> 
> However, this also reveals a flaw in the way we handle
> decr_pc_after_break.  Currently it's part of the architecture vector,
> which essentially means that we consider it part of the ISA.  However,
> the above shows that it also depends on the target interface.  So it
> seems we should make it possible for the target vector to override the
> default set by the architecture vector.
> 
> To people agree with this analysis?

The same problem pattern occures with software_single_step - the 
archititecture is incorrectly dictating the presence/absence of hardware 
single-step.

Both of these cases are used in infrun.c.  I think, in both cases, the 
logic should read something like:

	if (!target_has_<feature>_p ())
		gdb_assert (gdbarch_<feature-workaround>_p())
		use gdbarch_feature_workaround

Andrew