[ECOS] nested interrupt

[张 亮]

>From: Gary Thomas <gary@chez-thomas.org>
>To: ��<johnsonest@hotmail.com>
>CC: eCos Discussion <ecos-discuss@sources.redhat.com>
>Subject: Re: [ECOS] nested interrupt
>Date: 30 Jul 2002 07:02:23 -0600
>
>On Mon, 2002-07-29 at 19:05, ��wrote:
> > Hi,all!
> >   following question  is based on ARM arch.
> >
> > In ecos, when a lower level interrupt occur it will execute
> >
> > IRQ:
> >  // Note: I use this exception stack while saving the context because
> >  // the current SP does not seem to be always valid in this CPU mode.
> >  ldr sp,.__exception_stack // get good stack
> >  sub lr,lr,#4  // PC at time of interrupt
> >  stmfd sp!,{r0,fp,ip,lr}
> >  mrs r0,spsr
> >  stmfd sp!,{r0}
> >
> > handle_IRQ_or_FIQ:
> >  mov ip,sp   // save SP which will vanish with
> > ........
> > ........
> >
> >  mov sp,ip
> >  ldr lr,[sp,#armreg_pc]
> >  ldr r0,[sp,#armreg_cpsr]
> >  ldr ip,[sp,#armreg_ip]
> >  msr spsr,r0
> >  ldmfd sp,{r0-r10,fp}
> >  movs pc,lr   // restore PC from LR, CPSR from SPSR
> >
> >     And this time,
> >
> > a high level interrupt occurs
> >
> >     it will execute the above code again.
> > and the previous stack area will be destroy, the system
> > will be down, Is it right???
>
>No it shouldn't.  Interrupts can't be delivered until the 'movs'
>instruction completes, at which time the previous state will have
>been completely restored.
>
>Why do you think there is a problem?


There is my comment:
 
  My original mean is the lowerly priority may be broke when the high 
priority interrupt occurs 
and the register store in __exception_stack by lowerly priority interrupt 
may be destoryed 
 
If interrupts can not be delivered until the 'moves' instruction completes 
there is no mean of 'irq_level'. 
 
Could you like to explian why interrupt
can not be delivered until the 'moves' instruction completes.
 



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