[ECOS] RE: EP7212 I2S audio demo i2s_audio_fiq.S
Gary Thomas
gthomas@redhat.com
Fri Aug 25 09:25:00 GMT 2000
On 25-Aug-2000 AshCan@aol.com wrote:
> In file:
>
> /opt/ecos/ecos-1.3.1/packages/hal/arm/edb7xxx/v1_3_1/misc/i2s_audio_fiq.S,
>
> after the new samples have been fed to the DAI FIFO's, interrupt generating status is cleared by
> a write of data where the bits set to one clear their respective conditions:
>
> 10:
> ldr r11,=I2S_STAT // Clear status bits
> // ldr
> r10,=(I2S_STAT_RCTSR|I2S_STAT_RCRS|I2S_STAT_LCTSR|I2S_STAT_LCRSR|I2S_STAT_RCTNF|I2S_STAT_RCRNE|I2S
> _STAT_LCTNF|I2S_STAT_LCRNE)
> // ldr r10,=0xFFF0F
> ldr r10,=0x0FFF
> str r10,[r11]
>
> The statement below loading the clearing constant is odd since the I2S_STAT register only has
> data in the 12 ls bits. Also, the bits not being cleared are the FIFO ve and FIFO transmit
> underrun bits:
>
> // ldr r10,=0xFFF0F
>
> I was having problems with crashing when I repeated enabling the my DAC, playing audio, and
> disabling the DAC inside a while(1) loop.
>
> Modifying the statement to clear all 12 bits made the problem go away with no crashes so far in
> 17 hours. I do not have access to CVS yet, so someone please implement my change.
>
> ldr r10,=0x0FFF
>
Curious, your crashes may come from the extraneous bits. However, I purposefully
left out those four bits, just so the underrun conditions could be detected (for
diagnostic purposes). I'd suspect that this would work just as well as your change:
ldr r10,=0x0F0F
Note: this code is really just for demonstration purposes. It's not supported
and may contain errors. That said, of course we are always interested in feedback
and comments such as these.
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