[RFC] RISC-V: Support Zibi extension.
Jiawei
jiawei@iscas.ac.cn
Mon Mar 16 02:22:11 GMT 2026
Hi Jan,
Thanks for your review, will update in next version.
Best regards,
Jiawei
在 2026/3/13 20:40, Jan Beulich 写道:
> On 13.03.2026 13:30, Jiawei wrote:
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zibi.d
>> @@ -0,0 +1,16 @@
>> +#as: -march=rv64ic_zibi
>> +#source: zibi.s
>> +#objdump: -drw
>> +
>> +.*:[ ]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+ <target>:
>> +[ ]+[0-9a-f]+:[ ]+00042063[ ]+beqi[ ]+s0,0x0,0 <target>[ ]+0: R_RISCV_BRANCH .*
> While the immediate looks correct here, ...
>
>> +[ ]+[0-9a-f]+:[ ]+fe442ee3[ ]+beqi[ ]+s0,0x24,0 <target>[ ]+4: R_RISCV_BRANCH .*
>> +[ ]+[0-9a-f]+:[ ]+fe043ce3[ ]+bnei[ ]+s0,0x20,0 <target>[ ]+8: R_RISCV_BRANCH .*
>> +[ ]+[0-9a-f]+:[ ]+fe443ae3[ ]+bnei[ ]+s0,0x24,0 <target>[ ]+c: R_RISCV_BRANCH .*
> ... these three don't match ...
>
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zibi.s
>> @@ -0,0 +1,7 @@
>> + .text
>> +target:
>> + beqi x8, 0, target
>> + beqi x8, 4, target
>> + bnei x8, 0, target
>> + bnei x8, 4, target
> ... the input.
>
>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -527,6 +527,7 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"beqz", 0, INSN_CLASS_I, "s,p", MATCH_BEQ, MASK_BEQ|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"beq", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BEQZ, MASK_C_BEQZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"beq", 0, INSN_CLASS_I, "s,t,p", MATCH_BEQ, MASK_BEQ, match_opcode, INSN_CONDBRANCH },
>> +{"beqi", 0, INSN_CLASS_ZIBI, "s,>,p", MATCH_BEQI, MASK_BEQI, match_opcode, INSN_CONDBRANCH },
>> {"blez", 0, INSN_CLASS_I, "t,p", MATCH_BGE, MASK_BGE|MASK_RS1, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"bgez", 0, INSN_CLASS_I, "s,p", MATCH_BGE, MASK_BGE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"bge", 0, INSN_CLASS_I, "s,t,p", MATCH_BGE, MASK_BGE, match_opcode, INSN_CONDBRANCH },
> The new MATCH_BEQI imo wants to align with the adjacent MATCH_*.
>
>> @@ -543,6 +544,7 @@ const struct riscv_opcode riscv_opcodes[] =
>> {"bnez", 0, INSN_CLASS_I, "s,p", MATCH_BNE, MASK_BNE|MASK_RS2, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"bne", 0, INSN_CLASS_ZCA, "Cs,Cz,Cp", MATCH_C_BNEZ, MASK_C_BNEZ, match_opcode, INSN_ALIAS|INSN_CONDBRANCH },
>> {"bne", 0, INSN_CLASS_I, "s,t,p", MATCH_BNE, MASK_BNE, match_opcode, INSN_CONDBRANCH },
>> +{"bnei", 0, INSN_CLASS_ZIBI, "s,>,p", MATCH_BNEI, MASK_BNEI, match_opcode, INSN_CONDBRANCH },
>> {"addi", 0, INSN_CLASS_ZCA, "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_c_addi4spn, INSN_ALIAS },
>> {"addi", 0, INSN_CLASS_ZCA, "d,CU,Cj", MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, INSN_ALIAS },
>> {"addi", 0, INSN_CLASS_ZCA, "d,CU,z", MATCH_C_NOP, MASK_C_ADDI|MASK_RVC_IMM, match_c_nop, INSN_ALIAS },
> Here it wants to align with at least one of the two.
>
> And then, just like one can write ADD instead of ADDI, shouldn't this similarly
> be possible for these two new insns (possibly requiring a spec amendment)?
>
> Jan
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