[RFC] RISC-V: Support Zibi extension.

[Jan Beulich]

On 13.03.2026 13:40, Jan Beulich wrote:
> On 13.03.2026 13:30, Jiawei wrote:
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zibi.d
>> @@ -0,0 +1,16 @@
>> +#as: -march=rv64ic_zibi
>> +#source: zibi.s
>> +#objdump: -drw
>> +
>> +.*:[ 	]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+ <target>:
>> +[ 	]+[0-9a-f]+:[ 	]+00042063[ 	]+beqi[ 	]+s0,0x0,0 <target>[ 	]+0: R_RISCV_BRANCH	.*
> 
> While the immediate looks correct here, ...

Now having looked at the spec - this one isn't correct either. It ought
to be -1.

>> +[ 	]+[0-9a-f]+:[ 	]+fe442ee3[ 	]+beqi[ 	]+s0,0x24,0 <target>[ 	]+4: R_RISCV_BRANCH	.*
>> +[ 	]+[0-9a-f]+:[ 	]+fe043ce3[ 	]+bnei[ 	]+s0,0x20,0 <target>[ 	]+8: R_RISCV_BRANCH	.*
>> +[ 	]+[0-9a-f]+:[ 	]+fe443ae3[ 	]+bnei[ 	]+s0,0x24,0 <target>[ 	]+c: R_RISCV_BRANCH	.*
> 
> ... these three don't match ...
> 
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zibi.s
>> @@ -0,0 +1,7 @@
>> +	.text
>> +target:
>> +	beqi	x8, 0, target
>> +	beqi	x8, 4, target
>> +	bnei	x8, 0, target
>> +	bnei	x8, 4, target
> 
> ... the input.

And here 0 shouldn't be accepted (or converted to the register forms
of the insns).

Jan