[PATCH v3] opcodes: Fix BMASKI disassembly for immediate 32 on M*Core

[Jan Beulich]

On 20.01.2026 16:06, Michal Sobon wrote:
> The BMASKI instruction has three encoding variants (OMa, OMb, OMc).
> The OMa encoding (0x2C00, mask 0xFFF0) specifically represents
> BMASKI with immediate 32, encoded as IMM5=0.
> 
> Per Motorola M*Core specification: "An IMM5 value of 0 is interpreted
> as a value of 32."
> 
> Previously, all three variants extracted the immediate the same way,
> causing OMa to incorrectly display 0 instead of 32.
> 
> Before: 0x2c04 -> bmaski r4, 0
> After:  0x2c04 -> bmaski r4, 32
> 
> opcodes/
> 	* mcore-dis.c (print_insn_mcore): Handle OMa encoding to display
> 	immediate 32 instead of 0 for BMASKI.
> 
> gas/testsuite/
> 	* gas/mcore/allinsn.s: Add test for bmaski with immediate 32.
> 	Remove padding instructions and fix missing newline at end of file.
> 	* gas/mcore/allinsn.d: Update expected output.
> 
> Signed-off-by: Michal Sobon <msobon@hex-rays.com>
> ---
>  gas/testsuite/gas/mcore/allinsn.d | 5 +++--
>  gas/testsuite/gas/mcore/allinsn.s | 4 +---
>  opcodes/mcore-dis.c               | 5 ++++-
>  3 files changed, 8 insertions(+), 6 deletions(-)

Okay. You did check that ...

> --- a/gas/testsuite/gas/mcore/allinsn.d
> +++ b/gas/testsuite/gas/mcore/allinsn.d
> @@ -394,5 +394,6 @@ Disassembly of section \.text:
>  
>  0+0106 <zexth>:
>   106:	0164      	zexth	r4
> - 108:	0f00      	cmpne	r0, r0
> - 10a:	0f00      	cmpne	r0, r0
> +
> +0+0108 <Bmaski>:
> + 108:	2c04      	bmaski	r4, 32

... this change doesn't cause any testsuite fallout, neither for ELF nor
for PE/COFF? It is possible, after all, that the comment was only partly
wrong, meaning 4-byte alignment when saying 16.

I assume you don't have write access, and hence the patch will need
committing on your behalf?

Jan