[Valgrind-developers] [PATCH 1/2] x86: optimize XCHG to MOV for same-register forms

[Christian Ludloff]

> You mean for stepping 6? [...]

Thanks.

> Yep, that's in line with my recollections as per documentation.  I've
> never actually come across those chips though.  Clearly the PSE feature
> was a part of the WB cache RTL and they didn't bother stripping it off
> when adapting to the i486.

Agreed.

>>   https://www.sandpile.org/x86/cpuid.htm

Fwiw, the first word on the CPUID page ("Before") has
the link to Debs' excellent older summary.

>> Alas undefined OF for ROL/ROR >1 has seen numerous
>> different implementations/behaviors. See here:
>>
>>     https://www.sandpile.org/x86/flags.htm
>
> Ack, appreciate your effort to write down all the peculiarities, but that
> list does not go back to the older chips, where the limitation inevitably
> comes from.

Sure. Others can characterize the older behaviors.

My point was that OF for ROL/ROR >1 did indeed vary.

I wish the specs would have been tighter.

--
C.