[Valgrind-developers] [PATCH 1/2] x86: optimize XCHG to MOV for same-register forms

[Maciej W. Rozycki]

On Mon, 17 Aug 2026, Christian Ludloff wrote:

> > late 486 DX/2 stepping 5 which even has CPUID and
> > VME extensions (no 4MiB pages though; these landed
> > with stepping 6 only)
> 
> Can you please capture a short CPUID dump?  :)

 You mean for stepping 6?  There is not much to collect for a chip that 
old, but see <https://www.rcollins.org/articles/pvi1/pvi1.html> for what I 
gathered back in the day.  After ~30 years I have no access to that system 
anymore; it wasn't mine anyway and I can bet anything on that it does not 
exist anymore.

 As I recall this setup was actually documented in a late Intel i486 doc, 
but I'd have to chase it, probably in a hardcopy form too, as obviously I 
cannot quote the order number offhand.

> I got 480h (DX4) and 490h (DX4WB) dumps where PSE
> is a difference as well. And a 435h dump (no PSE)... but
> a 436h with PSE is a new one for me. See here:
> 
>   https://www.sandpile.org/x86/cpuid.htm (search 'PSE')

 Yep, that's in line with my recollections as per documentation.  I've 
never actually come across those chips though.  Clearly the PSE feature 
was a part of the WB cache RTL and they didn't bother stripping it off 
when adapting to the i486.

> > each and every ROR instruction did set OF according
> > to the result of the operation, even for the cases undefined
> 
> Alas undefined OF for ROL/ROR >1 has seen numerous
> different implementations/behaviors. See here:
> 
>     https://www.sandpile.org/x86/flags.htm

 Ack, appreciate your effort to write down all the peculiarities, but that 
list does not go back to the older chips, where the limitation inevitably 
comes from.

  Maciej