[PATCH] RISC-V: Add experimental support for Zvabd extension

[chen.zhongyao@zte.com.cn]

>From 621ed351372b8f20c8fade8cab89734f17a9dc72 Mon Sep 17 00:00:00 2001
From: Zhongyao Chen <chen.zhongyao@zte.com.cn>
Date: Sun, 7 Sep 2025 04:35:51 +0000
Subject: [PATCH] RISC-V: Add experimental support for Zvabd extension

This patch adds experimental support for the RISC-V Zvabd (Vector Absolute
Difference) extension, based on version 0.5 of the proposal.

The Zvabd instruction set specification can be found in the fast-track proposal:
https://lf-riscv.atlassian.net/wiki/spaces/VXXX/pages/166690866/Fast-Track+Proposal+for+integer+vector+absolute+difference+instructions

Note: This patch is just an initial prototype, mainly for early evaluation (e.g.
on FPGA) and to support fast-track proposal progress; it is not meant for
merging yet.

Co-authored-by: Yuke Tang <tang.yuke@zte.com.cn>
Signed-off-by: Zhongyao Chen <chen.zhongyao@zte.com.cn>
---
bfd/elfxx-riscv.c          |  6 ++++++
include/opcode/riscv-opc.h | 12 ++++++++++++
include/opcode/riscv.h     |  1 +
opcodes/riscv-opc.c        |  7 +++++++
4 files changed, 26 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 9163712967d..9fbd772260b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1302,6 +1302,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvksg", "+zvks,+zvkg", check_implicit_always},
{"zvksc", "+zvks,+zvbc", check_implicit_always},
{"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
+  {"zvabd", "+zvabd", check_implicit_always},

{"smaia", "+ssaia", check_implicit_always},
{"smcdeleg", "+ssccfg", check_implicit_always},
@@ -1546,6 +1547,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zcmop",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
{"zcmp",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
{"zcmt",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvabd",   ISA_SPEC_CLASS_DRAFT,   1, 0,  0 },
{"zclsd",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
{NULL, 0, 0, 0, 0}
};
@@ -2977,6 +2979,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zcmp");
case INSN_CLASS_ZCMT:
return riscv_subset_supports (rps, "zcmt");
+    case INSN_CLASS_ZVABD:
+      return riscv_subset_supports (rps, "zvabd");
case INSN_CLASS_SMCTR_OR_SSCTR:
return (riscv_subset_supports (rps, "smctr")
|| riscv_subset_supports (rps, "ssctr"));
@@ -3280,6 +3284,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "zcmp";
case INSN_CLASS_ZCMT:
return "zcmt";
+    case INSN_CLASS_ZVABD:
+      return "zvabd";
case INSN_CLASS_SMCTR_OR_SSCTR:
return _("smctr' or `ssctr");
case INSN_CLASS_ZILSD:
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1c649628390..20685ca6eff 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -1867,6 +1867,18 @@
#define MASK_VNCLIPWX  0xfc00707f
#define MATCH_VNCLIPWI  0xbc003057
#define MASK_VNCLIPWI  0xfc00707f
+//abs
+#define MATCH_VABS     0x48082057
+#define MASK_VABS      0xfc0ff07f
+#define MATCH_VABD     0x44002057
+#define MASK_VABD      0xfc00707f
+#define MATCH_VABDU    0x4c002057
+#define MASK_VABD      0xfc00707f
+#define MATCH_VWABDACC   0x54002057
+#define MASK_VWABDACC    0xfc00707f
+#define MATCH_VWABDACCU    0x58002057
+#define MASK_VWABDACC      0xfc00707f
+
#define MATCH_VFADDVV  0x00001057
#define MASK_VFADDVV  0xfc00707f
#define MATCH_VFADDVF  0x00005057
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 858fcce6871..8007bf09973 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -573,6 +573,7 @@ enum riscv_insn_class
INSN_CLASS_ZABHA,
INSN_CLASS_ZACAS,
INSN_CLASS_ZABHA_AND_ZACAS,
+  INSN_CLASS_ZVABD,
INSN_CLASS_H,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e6fe5e9afba..19dd1c512e0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2024,6 +2024,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"vnclip.wx",   0, INSN_CLASS_V,  "Vd,Vt,sVm", MATCH_VNCLIPWX, MASK_VNCLIPWX, match_opcode, 0 },
{"vnclip.wi",   0, INSN_CLASS_V,  "Vd,Vt,VjVm", MATCH_VNCLIPWI, MASK_VNCLIPWI, match_opcode, 0 },

+/*zvabd instructions.*/
+{"vabs.v",     0, INSN_CLASS_ZVABD,  "Vd,VtVm",  MATCH_VABS, MASK_VABS, match_opcode, 0 },
+{"vabd.vv",    0, INSN_CLASS_ZVABD,  "Vd,Vt,VsVm",  MATCH_VABD, MASK_VABD, match_opcode, 0 },
+{"vabdu.vv",    0, INSN_CLASS_ZVABD,  "Vd,Vt,VsVm",  MATCH_VABDU, MASK_VABD, match_opcode, 0 },
+{"vwabdacc.vv",  0, INSN_CLASS_ZVABD,  "Vd,Vt,VsVm", MATCH_VWABDACC, MASK_VWABDACC, match_opcode, 0 },
+{"vwabdaccu.vv",  0, INSN_CLASS_ZVABD,  "Vd,Vt,VsVm", MATCH_VWABDACCU, MASK_VWABDACC, match_opcode, 0 },
+
{"vfadd.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFADDVV, MASK_VFADDVV, match_opcode, 0},
{"vfadd.vf",   0, INSN_CLASS_ZVEF, "Vd,Vt,SVm", MATCH_VFADDVF, MASK_VFADDVF, match_opcode, 0},
{"vfsub.vv",   0, INSN_CLASS_ZVEF, "Vd,Vt,VsVm", MATCH_VFSUBVV, MASK_VFSUBVV, match_opcode, 0},
--
2.50.1