[PATCH 02/11] aarch64: Sort aarch64-sys-regs.def

[Alice Carlotti]

Fix obvious alphabetisation errors, and move s2pir_el2 and s2por_el1 to
the start of the "s" section to match the ordering in the Arm ARM.


diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index dd00c0fdad0bf4be707c946b92224e63d5ff1592..31ae528a7425b4514472a31fda38f835d312157d 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -425,17 +425,17 @@
   SYSREG ("fpexc32_el2",	CPENC (3,4,5,3,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("fpmr",		CPENC (3,3,4,4,2),	0,		AARCH64_FEATURE (FP8))
   SYSREG ("fpsr",		CPENC (3,3,4,4,1),	0,		AARCH64_NO_FEATURES)
+  SYSREG ("gcr_el1",		CPENC (3,0,1,0,6),	0,		AARCH64_FEATURE (MEMTAG))
+  SYSREG ("gcscr_el1",		CPENC (3,0,2,5,0),    	0,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el12",		CPENC (3,5,2,5,0),    	0,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el2",		CPENC (3,4,2,5,0),    	0,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el3",		CPENC (3,6,2,5,0),    	0,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscre0_el1",	CPENC (3,0,2,5,2),    	0,		AARCH64_FEATURE (GCS))
   SYSREG ("gcspr_el0",		CPENC (3,3,2,5,1),    	0,		AARCH64_FEATURE (GCS))
   SYSREG ("gcspr_el1",		CPENC (3,0,2,5,1),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcspr_el2",		CPENC (3,4,2,5,1),    	0,		AARCH64_FEATURE (GCS))
   SYSREG ("gcspr_el12",		CPENC (3,5,2,5,1),    	0,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcspr_el2",		CPENC (3,4,2,5,1),    	0,		AARCH64_FEATURE (GCS))
   SYSREG ("gcspr_el3",		CPENC (3,6,2,5,1),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcscre0_el1",	CPENC (3,0,2,5,2),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcscr_el1",		CPENC (3,0,2,5,0),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcscr_el2",		CPENC (3,4,2,5,0),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcscr_el12",		CPENC (3,5,2,5,0),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcscr_el3",		CPENC (3,6,2,5,0),    	0,		AARCH64_FEATURE (GCS))
-  SYSREG ("gcr_el1",		CPENC (3,0,1,0,6),	0,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("gmid_el1",		CPENC (3,1,0,0,4),	F_REG_READ,	AARCH64_FEATURE (MEMTAG))
   SYSREG ("gpcbw_el3",		CPENC (3,6,2,1,5),	0,		AARCH64_FEATURE (V9_5A))
   SYSREG ("gpccr_el3",		CPENC (3,6,2,1,6),	0,		AARCH64_NO_FEATURES)
@@ -625,6 +625,11 @@
   SYSREG ("oseccr_el1",		CPENC (2,0,0,6,2),	0,		AARCH64_NO_FEATURES)
   SYSREG ("oslar_el1",		CPENC (2,0,1,0,4),	F_REG_WRITE,	AARCH64_NO_FEATURES)
   SYSREG ("oslsr_el1",		CPENC (2,0,1,1,4),	F_REG_READ,	AARCH64_NO_FEATURES)
+  SYSREG ("pan",		CPENC (3,0,4,2,3),	0,		AARCH64_FEATURE (PAN))
+  SYSREG ("par_el1",		CPENC (3,0,7,4,0),	F_REG_128,	AARCH64_NO_FEATURES)
+  SYSREG ("pfar_el1",		CPENC (3,0,6,0,5),      0,              AARCH64_FEATURE (PFAR))
+  SYSREG ("pfar_el12",		CPENC (3,5,6,0,5),      0,              AARCH64_FEATURE (PFAR))
+  SYSREG ("pfar_el2",		CPENC (3,4,6,0,5),      0,              AARCH64_FEATURE (PFAR))
   SYSREG ("pir_el1",		CPENC (3,0,10,2,3),	0,		AARCH64_FEATURE (S1PIE))
   SYSREG ("pir_el12",		CPENC (3,5,10,2,3),	0,		AARCH64_FEATURE (S1PIE))
   SYSREG ("pir_el2",		CPENC (3,4,10,2,3),	0,		AARCH64_FEATURE (S1PIE))
@@ -632,11 +637,6 @@
   SYSREG ("pire0_el1",		CPENC (3,0,10,2,2),	0,		AARCH64_FEATURE (S1PIE))
   SYSREG ("pire0_el12",		CPENC (3,5,10,2,2),	0,		AARCH64_FEATURE (S1PIE))
   SYSREG ("pire0_el2",		CPENC (3,4,10,2,2),	0,		AARCH64_FEATURE (S1PIE))
-  SYSREG ("pan",		CPENC (3,0,4,2,3),	0,		AARCH64_FEATURE (PAN))
-  SYSREG ("par_el1",		CPENC (3,0,7,4,0),	F_REG_128,	AARCH64_NO_FEATURES)
-  SYSREG ("pfar_el1",		CPENC (3,0,6,0,5),      0,              AARCH64_FEATURE (PFAR))
-  SYSREG ("pfar_el12",		CPENC (3,5,6,0,5),      0,              AARCH64_FEATURE (PFAR))
-  SYSREG ("pfar_el2",		CPENC (3,4,6,0,5),      0,              AARCH64_FEATURE (PFAR))
   SYSREG ("pmbidr_el1",		CPENC (3,0,9,10,7),	F_REG_READ,	AARCH64_FEATURE (PROFILE))
   SYSREG ("pmblimitr_el1",	CPENC (3,0,9,10,0),	0,		AARCH64_FEATURE (PROFILE))
   SYSREG ("pmbmar_el1",		CPENC (3,0,9,10,5),	0,		AARCH64_FEATURES (2, PROFILE, V9_5A))
@@ -860,6 +860,8 @@
   SYSREG ("rvbar_el1",		CPENC (3,0,12,0,1),	F_REG_READ,	AARCH64_NO_FEATURES)
   SYSREG ("rvbar_el2",		CPENC (3,4,12,0,1),	F_REG_READ,	AARCH64_NO_FEATURES)
   SYSREG ("rvbar_el3",		CPENC (3,6,12,0,1),	F_REG_READ,	AARCH64_NO_FEATURES)
+  SYSREG ("s2pir_el2",		CPENC (3,4,10,2,5),	0,		AARCH64_FEATURE (S2PIE))
+  SYSREG ("s2por_el1",		CPENC (3,0,10,2,5),	0,		AARCH64_FEATURE (S2POE))
   SYSREG ("scr_el3",		CPENC (3,6,1,1,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("sctlr_el1",		CPENC (3,0,1,0,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("sctlr_el12",		CPENC (3,5,1,0,0),	0,		AARCH64_FEATURE (V8_1A))
@@ -983,8 +985,6 @@
   SYSREG ("spsr_und",		CPENC (3,4,4,3,2),	0,		AARCH64_NO_FEATURES)
   SYSREG ("ssbs",		CPENC (3,3,4,2,6),	0,		AARCH64_FEATURE (SSBS))
   SYSREG ("svcr",		CPENC (3,3,4,2,2),	0,		AARCH64_FEATURE (SME))
-  SYSREG ("s2pir_el2",		CPENC (3,4,10,2,5),	0,		AARCH64_FEATURE (S2PIE))
-  SYSREG ("s2por_el1",		CPENC (3,0,10,2,5),	0,		AARCH64_FEATURE (S2POE))
   SYSREG ("tco",		CPENC (3,3,4,2,7),	0,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("tcr_el1",		CPENC (3,0,2,0,2),	0,		AARCH64_NO_FEATURES)
   SYSREG ("tcr_el12",		CPENC (3,5,2,0,2),	0,		AARCH64_FEATURE (V8_1A))