[PATCH 3/7] RISC-V: Add support for XAndesVSIntLoad extension
Ethan Y. C. Liang
ycl669@andestech.com
Tue Nov 18 09:13:46 GMT 2025
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVSIntLoad extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVSIntLoad as an additional ISA extension
for Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvsintload string.
* testsuite/gas/riscv/x-andes-vsintload.d: New test.
* testsuite/gas/riscv/x-andes-vsintload.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVSINTLOAD.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add vector load instructions for INT4 data
into 8-bit elements.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vsintload.d | 16 ++++++++++++++++
gas/testsuite/gas/riscv/x-andes-vsintload.s | 7 +++++++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-andes-vsintload.d
create mode 100644 gas/testsuite/gas/riscv/x-andes-vsintload.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 28aeb157f3e..c09e81c8e45 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1611,6 +1611,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
{"xandesbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xandesvbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvsintload", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -3001,6 +3002,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xandesbfhcvt");
case INSN_CLASS_XANDESVBFHCVT:
return riscv_subset_supports (rps, "xandesvbfhcvt");
+ case INSN_CLASS_XANDESVSINTLOAD:
+ return riscv_subset_supports (rps, "xandesvsintload");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3316,6 +3319,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xandesbfhcvt";
case INSN_CLASS_XANDESVBFHCVT:
return "xandesvbfhcvt";
+ case INSN_CLASS_XANDESVSINTLOAD:
+ return "xandesvsintload";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index aaca300be88..7878c520d35 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -777,6 +777,11 @@ The XAndesVBFHCvt extension provides vector BF16 and FP32 conversion instruction
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVSIntLoad
+The XAndesVSIntLoad extension provides vector load instructions for INT4 data into 8-bit elements.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index d8e5cd61a40..8b907260af9 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -156,6 +156,7 @@ All available -march extensions for RISC-V:
supm 1.0
xandesbfhcvt 5.0
xandesvbfhcvt 5.0
+ xandesvsintload 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vsintload.d b/gas/testsuite/gas/riscv/x-andes-vsintload.d
new file mode 100644
index 00000000000..8f32c8a4812
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vsintload.d
@@ -0,0 +1,16 @@
+#as: -march=rv32i_xandesvsintload
+#source: x-andes-vsintload.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0625425b[ ]+nds\.vln8\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0625425b[ ]+nds\.vln8\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0425425b[ ]+nds\.vln8\.v[ ]+v4,\(a0\),v0\.t
+[ ]+[0-9a-f]+:[ ]+0635425b[ ]+nds\.vlnu8\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0635425b[ ]+nds\.vlnu8\.v[ ]+v4,\(a0\)
+[ ]+[0-9a-f]+:[ ]+0435425b[ ]+nds\.vlnu8\.v[ ]+v4,\(a0\),v0\.t
diff --git a/gas/testsuite/gas/riscv/x-andes-vsintload.s b/gas/testsuite/gas/riscv/x-andes-vsintload.s
new file mode 100644
index 00000000000..b858eaa66ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vsintload.s
@@ -0,0 +1,7 @@
+target:
+ nds.vln8.v v4, (a0)
+ nds.vln8.v v4, 0(a0)
+ nds.vln8.v v4, (a0), v0.t
+ nds.vlnu8.v v4, (a0)
+ nds.vlnu8.v v4, 0(a0)
+ nds.vlnu8.v v4, (a0), v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 0243cba6af9..d47e5f871e1 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2530,6 +2530,11 @@
#define MASK_NDS_VFWCVT_S_BF16 0xfe0ff07f
#define MATCH_NDS_VFNCVT_BF16_S 0xc05b
#define MASK_NDS_VFNCVT_BF16_S 0xfe0ff07f
+/* Vendor-specific (Andes) XAndesVSIntLoad instructions. */
+#define MATCH_NDS_VLN8_V 0x420405b
+#define MASK_NDS_VLN8_V 0xfdf0707f
+#define MATCH_NDS_VLNU8_V 0x430405b
+#define MASK_NDS_VLNU8_V 0xfdf0707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -4852,6 +4857,9 @@ DECLARE_INSN(nds_fcvt_bf16_s, MATCH_NDS_FCVT_BF16_S, MASK_NDS_FCVT_BF16_S)
/* Vendor-specific (Andes) XAndesVBFHCvt instructions. */
DECLARE_INSN(nds_vfwcvt_s_bf16, MATCH_NDS_VFWCVT_S_BF16, MASK_NDS_VFWCVT_S_BF16)
DECLARE_INSN(nds_vfncvt_bf16_s, MATCH_NDS_VFNCVT_BF16_S, MASK_NDS_VFNCVT_BF16_S)
+/* Vendor-specific (Andes) XAndesVSIntLoad instructions. */
+DECLARE_INSN(nds_vln8_v, MATCH_NDS_VLN8_V, MASK_NDS_VLN8_V)
+DECLARE_INSN(nds_vlnu8_v, MATCH_NDS_VLNU8_V, MASK_NDS_VLNU8_V)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 424450b7060..788029d4240 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -576,6 +576,7 @@ enum riscv_insn_class
INSN_CLASS_H,
INSN_CLASS_XANDESBFHCVT,
INSN_CLASS_XANDESVBFHCVT,
+ INSN_CLASS_XANDESVSINTLOAD,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fd3f14ffe06..0f7d8f00825 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2386,6 +2386,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.vfwcvt.s.bf16", 0, INSN_CLASS_XANDESVBFHCVT, "Vd,Vt", MATCH_NDS_VFWCVT_S_BF16, MASK_NDS_VFWCVT_S_BF16, match_opcode, 0},
{"nds.vfncvt.bf16.s", 0, INSN_CLASS_XANDESVBFHCVT, "Vd,Vt", MATCH_NDS_VFNCVT_BF16_S, MASK_NDS_VFNCVT_BF16_S, match_opcode, 0},
+/* Vendor-specific (Andes) XAndesVSIntLoad instructions. */
+{"nds.vln8.v", 0, INSN_CLASS_XANDESVSINTLOAD, "Vd,0(s)Vm", MATCH_NDS_VLN8_V, MASK_NDS_VLN8_V, match_opcode, INSN_DREF},
+{"nds.vlnu8.v", 0, INSN_CLASS_XANDESVSINTLOAD, "Vd,0(s)Vm", MATCH_NDS_VLNU8_V, MASK_NDS_VLNU8_V, match_opcode, INSN_DREF},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
--
2.49.0
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