[PATCH 2/7] RISC-V: Add support for XAndesVBFHCvt extension
Ethan Y. C. Liang
ycl669@andestech.com
Tue Nov 18 09:13:45 GMT 2025
Spec: https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support for
XAndesVBFHCvt extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Note XAndesVBFHCvt as an additional ISA extension
for Andes.
* testsuite/gas/riscv/march-help.l: Add xandesvbfhcvt string.
* testsuite/gas/riscv/x-andes-vbfhcvt.d: New test.
* testsuite/gas/riscv/x-andes-vbfhcvt.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h: Add corresponding MATCH and MASK instruction
opcode macros.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_XANDESVBFHCVT.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcode): Add vector BF16 and FP32 conversion
instructions.
Signed-off-by: Ethan Y. C. Liang <ycl669@andestech.com>
---
bfd/elfxx-riscv.c | 5 +++++
gas/doc/c-riscv.texi | 5 +++++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/x-andes-vbfhcvt.d | 12 ++++++++++++
gas/testsuite/gas/riscv/x-andes-vbfhcvt.s | 3 +++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
8 files changed, 39 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/x-andes-vbfhcvt.d
create mode 100644 gas/testsuite/gas/riscv/x-andes-vbfhcvt.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 616e46c320f..28aeb157f3e 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1610,6 +1610,7 @@ static const struct riscv_supported_ext riscv_supported_std_zxm_ext[] =
static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{
{"xandesbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
+ {"xandesvbfhcvt", ISA_SPEC_CLASS_DRAFT, 5, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbitmanip", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2998,6 +2999,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "h");
case INSN_CLASS_XANDESBFHCVT:
return riscv_subset_supports (rps, "xandesbfhcvt");
+ case INSN_CLASS_XANDESVBFHCVT:
+ return riscv_subset_supports (rps, "xandesvbfhcvt");
case INSN_CLASS_XCVALU:
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVBI:
@@ -3311,6 +3314,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("h");
case INSN_CLASS_XANDESBFHCVT:
return "xandesbfhcvt";
+ case INSN_CLASS_XANDESVBFHCVT:
+ return "xandesvbfhcvt";
case INSN_CLASS_XCVALU:
return "xcvalu";
case INSN_CLASS_XCVBI:
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 146b843e107..aaca300be88 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -772,6 +772,11 @@ The XAndesBFHCvt extension provides scalar BF16 and FP32 conversion instructions
It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+@item XAndesVBFHCvt
+The XAndesVBFHCvt extension provides vector BF16 and FP32 conversion instructions.
+
+It is documented in @url{https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf}.
+
@item XCvAlu
The XCvAlu extension provides instructions for general ALU operations.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index dff841f69d4..d8e5cd61a40 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -155,6 +155,7 @@ All available -march extensions for RISC-V:
sspm 1.0
supm 1.0
xandesbfhcvt 5.0
+ xandesvbfhcvt 5.0
xcvalu 1.0
xcvbi 1.0
xcvbitmanip 1.0
diff --git a/gas/testsuite/gas/riscv/x-andes-vbfhcvt.d b/gas/testsuite/gas/riscv/x-andes-vbfhcvt.d
new file mode 100644
index 00000000000..57b86661eb9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vbfhcvt.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xandesvbfhcvt
+#source: x-andes-vbfhcvt.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0080425b[ ]+nds\.vfwcvt\.s\.bf16[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+0080c25b[ ]+nds\.vfncvt\.bf16\.s[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/x-andes-vbfhcvt.s b/gas/testsuite/gas/riscv/x-andes-vbfhcvt.s
new file mode 100644
index 00000000000..1e318396de3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-andes-vbfhcvt.s
@@ -0,0 +1,3 @@
+target:
+ nds.vfwcvt.s.bf16 v4, v8
+ nds.vfncvt.bf16.s v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index d6b230c9f3e..0243cba6af9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2525,6 +2525,11 @@
#define MASK_NDS_FCVT_S_BF16 0xfe0ff07f
#define MATCH_NDS_FCVT_BF16_S 0x1c05b
#define MASK_NDS_FCVT_BF16_S 0xfe0ff07f
+/* Vendor-specific (Andes) XAndesVBFHCvt instructions. */
+#define MATCH_NDS_VFWCVT_S_BF16 0x405b
+#define MASK_NDS_VFWCVT_S_BF16 0xfe0ff07f
+#define MATCH_NDS_VFNCVT_BF16_S 0xc05b
+#define MASK_NDS_VFNCVT_BF16_S 0xfe0ff07f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@@ -4844,6 +4849,9 @@ DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
/* Vendor-specific (Andes) XAndesBFHCvt instructions. */
DECLARE_INSN(nds_fcvt_s_bf16, MATCH_NDS_FCVT_S_BF16, MASK_NDS_FCVT_S_BF16)
DECLARE_INSN(nds_fcvt_bf16_s, MATCH_NDS_FCVT_BF16_S, MASK_NDS_FCVT_BF16_S)
+/* Vendor-specific (Andes) XAndesVBFHCvt instructions. */
+DECLARE_INSN(nds_vfwcvt_s_bf16, MATCH_NDS_VFWCVT_S_BF16, MASK_NDS_VFWCVT_S_BF16)
+DECLARE_INSN(nds_vfncvt_bf16_s, MATCH_NDS_VFNCVT_BF16_S, MASK_NDS_VFNCVT_BF16_S)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 34c3fb8c9a1..424450b7060 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -575,6 +575,7 @@ enum riscv_insn_class
INSN_CLASS_ZABHA_AND_ZACAS,
INSN_CLASS_H,
INSN_CLASS_XANDESBFHCVT,
+ INSN_CLASS_XANDESVBFHCVT,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVBI,
INSN_CLASS_XCVBITMANIP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c8458d550b3..fd3f14ffe06 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2382,6 +2382,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"nds.fcvt.s.bf16", 0, INSN_CLASS_XANDESBFHCVT, "D,T", MATCH_NDS_FCVT_S_BF16, MASK_NDS_FCVT_S_BF16, match_opcode, 0},
{"nds.fcvt.bf16.s", 0, INSN_CLASS_XANDESBFHCVT, "D,T", MATCH_NDS_FCVT_BF16_S, MASK_NDS_FCVT_BF16_S, match_opcode, 0},
+/* Vendor-specific (Andes) XAndesVBFHCvt instructions. */
+{"nds.vfwcvt.s.bf16", 0, INSN_CLASS_XANDESVBFHCVT, "Vd,Vt", MATCH_NDS_VFWCVT_S_BF16, MASK_NDS_VFWCVT_S_BF16, match_opcode, 0},
+{"nds.vfncvt.bf16.s", 0, INSN_CLASS_XANDESVBFHCVT, "Vd,Vt", MATCH_NDS_VFNCVT_BF16_S, MASK_NDS_VFNCVT_BF16_S, match_opcode, 0},
+
/* Vendor-specific (CORE-V) Xcvmac instructions. */
{"cv.mac", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MAC, MASK_CV_MAC, match_opcode, 0},
{"cv.msu", 0, INSN_CLASS_XCVMAC, "d,s,t", MATCH_CV_MSU, MASK_CV_MSU, match_opcode, 0},
--
2.49.0
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