[PATCH] Add AMD znver6 processor support

[Jiang, Haochen]

> From: Kalvakuntla, Umesh <Umesh.Kalvakuntla@amd.com>
> Sent: Friday, November 14, 2025 10:24 PM
> 
> diff --git a/gas/testsuite/gas/i386/arch-16.s b/gas/testsuite/gas/i386/arch-
> 16.s
> new file mode 100644
> index 00000000000..58d80b5bc88
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-16.s
> @@ -0,0 +1,8 @@
> +# Test -march=
> +	.text
> +
> +	vbmacor16x16x16 %ymm1, %ymm2, %ymm3	#AVX512BMM
> +	vbcstnebf162ps (%edx), %xmm1		#AVX_NE_CONVERT
> +        vpmadd52huq %xmm1, %xmm1, %xmm2		#AVX_IFMA
> +	vpdpbssd %ymm1, %ymm2, %ymm3		#AVX_VNNI_INT8
> +	vaddph %zmm1, %zmm2, %zmm3		#AVX512-FP16

The padding seems messed up in .patch file is because sometimes you are
using tabs at the beginning, while sometimes spaces. Please use tabs.

> diff --git a/gas/testsuite/gas/i386/avx512_bmm.d
> b/gas/testsuite/gas/i386/avx512_bmm.d
> new file mode 100644
> index 00000000000..989dfd6c003
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/avx512_bmm.d
> @@ -0,0 +1,42 @@
> +#objdump: -dw
> +#name: i386 AVX512_BMM insns
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <bmm>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80
> d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -
> 0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16
> 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -
> 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80
> d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -
> 0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16
> 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -
> 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80
> d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -
> 0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16
> 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -
> 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80
> d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -
> 0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16
> 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -
> 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrev %xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81
> d1[\s]*vbitrev %xmm1,%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%xmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrev
> 0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 52 80[\s]*vbitrev -
> 0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrev %ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81
> d1[\s]*vbitrev %ymm1,%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrev
> 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 50 80[\s]*vbitrev -
> 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrev %zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81
> d1[\s]*vbitrev %zmm1,%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrev -
> 0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrev
> 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 52 80[\s]*vbitrev -
> 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> \ No newline at end of file

Please add "#pass" at the end for all .d file to make sure it passed
on all the OS. Also please avoid " No newline at end of file ".

> diff --git a/gas/testsuite/gas/i386/x86-64-arch-6.s
> b/gas/testsuite/gas/i386/x86-64-arch-6.s
> new file mode 100644
> index 00000000000..58d80b5bc88
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-arch-6.s
> @@ -0,0 +1,8 @@
> +# Test -march=
> +	.text
> +
> +	vbmacor16x16x16 %ymm1, %ymm2, %ymm3	#AVX512BMM
> +	vbcstnebf162ps (%edx), %xmm1		#AVX_NE_CONVERT
> +        vpmadd52huq %xmm1, %xmm1, %xmm2		#AVX_IFMA
> +	vpdpbssd %ymm1, %ymm2, %ymm3		#AVX_VNNI_INT8
> +	vaddph %zmm1, %zmm2, %zmm3		#AVX512-FP16

As Jan said in the previous review, I also doubt the test would pass even w/o
-march=znver6 since unlike GCC, Binutils is ISA default on mode.

> diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
> index bfdcfb29fdd..997a61033a3 100644
> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> @@ -524,3 +524,13 @@
>    {
>      { "vmovw",	{ EXwS, XMScalar }, 0 },
>    },
> +  /* EVEX_W_MAP6_80 */
> +  {
> +    { "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
> +    { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
> +  },

Could you help align the "{ XM, Vex, EXx }" part, it is typically
a tab between inst and this part. (I know there are some messed
up in the file, mostly introduced in AVX512FP16, but please don't
make it worse.)

> +  /* EVEX_W_MAP6_81 */
> +  {
> +    { "vbitrev", { XM, EXx }, NO_PREFIX },
> +    { Bad_Opcode }
> +  }
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index bc86f2befbb..dbea02f1a9f 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -208,6 +210,8 @@ static const dependency isa_dependencies[] =
>      "AVX512BW" },
>    { "AVX512_VP2INTERSECT",
>      "AVX512F" },
> +  { "AVX512_BMM",
> +    "AVX512VL|AVX512BW" },

My comment misleads you. Jan is right, we do not need AVX512VL here.
VL would be checked when using EVEX xmm/ymms. Since there are also
zmm insts that do not need VL at all, implying VL here is wrong.

Another question is, will there be official documentation available in the
near future? For Binutils, encoding info provided in patch is probably ok
if you are with strong confidence nothing would change. But for GCC,
which needs runtime test, the info is not enough for only those provided.
Pseudocode are needed.

Thx,
Haochen